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Resilient die-stacked DRAM caches

Jaewoong Sim, Gabriel H. Loh, Vilas Sridharan, Mike O'Connor
2013 Proceedings of the 40th Annual International Symposium on Computer Architecture - ISCA '13  
Die-stacked DRAM can provide large amounts of in-package, highbandwidth cache storage.  ...  In this paper, we present a DRAM cache organization that uses errorcorrecting codes (ECCs), strong checksums (CRCs), and dirty data duplication to detect and correct a wide range of stacked DRAM failures  ...  Die-stacked DRAM Die-stacked DRAM consists of one or more layers of DRAM with a very-wide data interface connecting the DRAM stack to whatever it is stacked with (e.g., a processor die).  ... 
doi:10.1145/2485922.2485958 dblp:conf/isca/SimLSO13 fatcat:n6uix5stxnag7dambcoqhtoy4a

Parity Helix: Efficient protection for single-dimensional faults in multi-dimensional memory systems

Xun Jian, Vilas Sridharan, Rakesh Kumar
2016 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)  
Emerging die-stacked DRAMs provide several factors higher bandwidth and energy efficiency than 2D DRAMs, making them excellent candidates for future memory systems.  ...  To be deployed in server and high-performance computing systems, however, die-stacked DRAMs need to provide equivalent or better reliability than existing 2D DRAMs.  ...  Several recent works on error resilience for die-stacked DRAMs have proposed RAID-like schemes for die-stacked DRAMs.  ... 
doi:10.1109/hpca.2016.7446094 dblp:conf/hpca/JianS016 fatcat:7diqfeziqrf2nkg37wskf6ngoe

Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures

Prashant J. Nair, David A. Roberts, Moinuddin K. Qureshi
2014 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture  
Our evaluations with real-world data for DRAM failures show that Citadel provides performance and power similar to maintaining the entire cache line in the same bank, and yet provides 700x higher reliability  ...  stacked memory from large-granularity failures.  ...  We also thank Vilas Sridharan for his comments on DRAM scaling and FIT rates, and the members of our research group at Georgia Tech and AMD Research for providing insightful feedback.  ... 
doi:10.1109/micro.2014.57 dblp:conf/micro/NairRQ14 fatcat:jz7wfqb34vblflr46pg57rlz3y

A Survey Of Techniques for Architecting DRAM Caches

Sparsh Mittal, Jeffrey S. Vetter
2016 IEEE Transactions on Parallel and Distributed Systems  
In face of increasing cache capacity demands, researchers have now explored DRAM, which was conventionally considered synonymous to main memory, for designing large last level caches.  ...  We believe that this paper will be very helpful to researchers for gaining insights into the potential, tradeoffs and challenges of DRAM caches.  ...  Ensuring resilience to soft-errors and process-variation Given the high reliability requirement of die-stacked DRAMs, Sim et al.  ... 
doi:10.1109/tpds.2015.2461155 fatcat:tqg5hgv64bfnbf6m5c6v4mh5sa

Architectural Techniques to Enable Reliable and Scalable Memory Systems [article]

Prashant J. Nair
2017 arXiv   pre-print
Furthermore, each DRAM die within the stacked memory is also susceptible to large-granularity failures.  ...  Similarly, two prior works try to address stacked memory reliability without considering TSV faults. The first prior work proposes techniques to reliably architect stacked DRAM caches [110] .  ...  Power Accessing multiple banks or channels to satisfy every memory request also has the disadvantage that it consumes significantly higher power. 3DP design allows Citadel to place the entire cache line  ... 
arXiv:1704.03991v1 fatcat:e4i5pbtuujagnprene3wwv3un4

Exploring DRAM organizations for energy-efficient and resilient exascale memories

Bharan Giridhar, David Blaauw, Michael Cieslak, Deepankar Duggal, Ronald Dreslinski, Hsing Min Chen, Robert Patti, Betina Hold, Chaitali Chakrabarti, Trevor Mudge
2013 Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis on - SC '13  
Although specialized DRAM memories have been reorganized to reduce power through 3D-stacking or row buffer resizing, their implications on fault tolerance have not been considered.  ...  The proposed 3D-stacked memory uses a page size of 4kb and consumes 5.1pJ/bit based on simulations with NEK5000 benchmarks.  ...  Each 32Gb 3D chip consists of 8 4Gb DRAM memory dies stacked on top of a logic die. The organization of the 4Gb DRAM die is based on Tezzaron's existing Octopus [3] DRAM solution.  ... 
doi:10.1145/2503210.2503215 dblp:conf/sc/GiridharCDDCPHCMB13 fatcat:46x7e3nyabh35ioo7ysdy7vcp4

Balancing reliability, cost, and performance tradeoffs with FreeFault

Dong Wan Kim, Mattan Erez
2015 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)  
Because it requires a very modest portion of the cache (as small as 8KB) to cover a large fraction of DRAM faults, FreeFault has almost no impact on performance.  ...  In this paper, we present FreeFault as a hardware-only, transparent, and nearlyfree resilience mechanism that is implemented entirely within a processor and can tolerate the majority of DRAM faults.  ...  Fault Caches have been proposed within the DRAM die or package to be used as spare locations for memory retirement and repair [58] .  ... 
doi:10.1109/hpca.2015.7056053 dblp:conf/hpca/KimE15 fatcat:mcj3zvmqkrdatdziyvexyof6w4

Reliability and Performance Trade-off Study of Heterogeneous Memories

Manish Gupta, David Roberts, Mitesh Meswani, Vilas Sridharan, Dean Tullsen, Rajesh Gupta
2016 Proceedings of the Second International Symposium on Memory Systems - MEMSYS '16  
Researchers have explored methods and organizations to optimize performance by increasing the access rate to faster die-stacked memory.  ...  Heterogeneous memories, organized as die-stacked in-package and off-package memory, have been a focus of attention by the computer architects to improve memory bandwidth and capacity.  ...  DRAM on die-stacked memory can provide as much as 128 bits per cycle, and the entire cache line is fetched from a single DRAM chip.  ... 
doi:10.1145/2989081.2989113 dblp:conf/memsys/GuptaRMSTG16 fatcat:275k25jrpfaqpdpuvi3af3mug4

MAGE: Adaptive Granularity and ECC for resilient and power efficient memory systems

Sheng Li, Doe Hyun Yoon, Ke Chen, Jishen Zhao, Jung Ho Ahn, Jay B. Brockman, Yuan Xie, Norman P. Jouppi
2012 2012 International Conference for High Performance Computing, Networking, Storage and Analysis  
Providing strong error tolerance in memory usually requires a wide memory channel that incurs a large access granularity (hence, a large cache line).  ...  Resiliency is one of the toughest challenges in highperformance computing, and memory accounts for a significant fraction of errors.  ...  As the modeling results in Table III indicate, a 64-core MAGE processor, with a 176 mm 2 die size, can provide an aggregate throughput of 640 GFLOPS.  ... 
doi:10.1109/sc.2012.73 dblp:conf/sc/LiYCZABXJ12 fatcat:bp6rb3daqbfd3oiofmgad4uu7a

2019 Index IEEE Computer Architecture Letters Vol. 18

2020 IEEE computer architecture letters  
-June 2019 26-29 Integrated circuits Power Profiling of Modern Die-Stacked Memory.  ...  -June 2019 6-9 Memory management Exploiting OS-Level Memory Offlining for DRAM Power Management. Lee, S., +, LCA July-Dec. 2019 141-144 Power Profiling of Modern Die-Stacked Memory.  ... 
doi:10.1109/lca.2020.2964168 fatcat:pv44gn35vrb75jabsid7x62xpm

Leveraging 3D Technology for Improved Reliability

Niti Madan, Rajeev Balasubramonian
2007 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)  
We comprehensively evaluate design choices for this second die, including the effects of L2 cache organization, deep pipelining, and frequency.  ...  An increase in within-die and die-to-die parameter variations has also led to a greater number of dynamic timing errors.  ...  of heterogeneous dies: A concrete application of this approach is the 3D stacking of DRAM chips upon large-scale CMPs.  ... 
doi:10.1109/micro.2007.31 dblp:conf/micro/MadanB07 fatcat:fujfszg25nfxncpwik2kxfkkh4

Leveraging 3D Technology for Improved Reliability

Niti Madan, Rajeev Balasubramonian
2007 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
We comprehensively evaluate design choices for this second die, including the effects of L2 cache organization, deep pipelining, and frequency.  ...  An increase in within-die and die-to-die parameter variations has also led to a greater number of dynamic timing errors.  ...  of heterogeneous dies: A concrete application of this approach is the 3D stacking of DRAM chips upon large-scale CMPs.  ... 
doi:10.1109/micro.2007.4408258 fatcat:prpycpg3wfgwbnhe5tqneewoli

Abstract Machine Models and Proxy Architectures for Exascale Computing

J.A. Ang, R.F. Barrett, R.E. Benner, D. Burke, C. Chan, J. Cook, D. Donofrio, S.D. Hammond, K.S. Hemmert, S.M. Kelly, H. Le, V.J. Leung (+6 others)
2014 2014 Hardware-Software Co-Design for High Performance Computing  
of redesigned memory die).  ...  Cache 256KB-2MB Per Core L3 Cache 64MB-128MB Likely to be shared amongst groups of cores/accelerators L4 Cache 2GB-4GB Not on all systems, likely to be off-package embedded- DRAM Memory System  ...  Likewise, not all parameters are useful for application developers, such as bandwidth of each level of the cache structure.  ... 
doi:10.1109/co-hpc.2014.4 dblp:conf/sc/AngBBBCCDHHKLLR14 fatcat:sot6sfvdhbcwfbspps77auhwum

Disintegrated control for energy-efficient and heterogeneous memory systems

Tae Jun Ham, B. K. Chelepalli, Neng Xue, B. C. Lee
2013 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)  
We apply these strategies to architect a novel heterogeneous DRAM / PCM system. Finally, we present mechanisms for power-efficient data movement.  ...  HMC is made for 3D-stacked DRAM connected to the processor die via TSV interconnects.  ...  Udipi et al. shift protocol implementation to a control die in 3D-stacked memory. Because stacks' controllers share a bus, a reservation protocol is required [40] .  ... 
doi:10.1109/hpca.2013.6522338 dblp:conf/hpca/HamCXL13 fatcat:cugwd6ptxbh3nmpot6wsdph22i

ZEM: Zero-cycle Bit-masking Module for Deep Learning Refresh-less DRAM

Duy-Thanh Nguyen, Nhut-Minh Ho, Minh-Son Le, Weng-Fai Wong, Ik-Joon Chang
2021 IEEE Access  
There are several DRAM types such as LPDDR, DDR, and HBM, implemented as system-in-package (SiP), dual inline memory module (DIMM), and stacked-die, respectively.  ...  miss rates on various last level cache sizes, 64-byte cache lines FIGURE 13 . 13 Processing time of ZEM architecture on different DRAM types FIGURE 14.  ... 
doi:10.1109/access.2021.3088893 fatcat:goa2xnsgnfa6bai5x2bujilnxa
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