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Design of the coarse-grained reconfigurable architecture DART with on-line error detection

S.M.A.H. Jafri, S.J. Piestrak, O. Sentieys, S. Pillement
2014 Microprocessors and microsystems  
Most parts of the data paths and of the local memory of DART are protected using residue code modulo 3, whereas only the logic unit is protected using duplication with comparison.  ...  Introducing one extra pipeline stage in the self-checking version of the basic arithmetic blocks has allowed to significantly reduce the delay overhead compared to our previous design. (S.M.A.H.  ...  Residue multiplier mod 3 The residue multiplier mod 3 jZj 3 ¼ jXj 3 Á jYj 3 3 ¼ ðz 1 z 0 Þ is a part of the M/A circuit mod 3 needed by the self-checking M/A unit.  ... 
doi:10.1016/j.micpro.2013.12.004 fatcat:emch7jwjkrbqhfjxbthq6wx6qu

Design of fault-tolerant computers

Algirdas Avižienis
1967 Proceedings of the November 14-16, 1967, fall joint computer conference on - AFIPS '67 (Fall)  
Causes and symptoms of logic faults in digital systems.  ...  All arithmetic control is contained in the MAP; an input consists of an operation code (add, subtract, multiply, divide) followed by a coded operand, and the output is a coded result followed by a 2-out-of  ...  The Design of Fault-tolerant Computers 742 auxiliary unit stores the same input words as its main unit.  ... 
doi:10.1145/1465611.1465708 dblp:conf/afips/Avizienis67 fatcat:wtu2n5wp2vdxpe2acea6rbj4zi

FT-EALU: Fault Tolerant Arithmetic and Logic Unit for Critical Embedded and Real time Systems [article]

Athena Abdi, Sina Shahoveisi
2022 arXiv   pre-print
In this paper, a fault-tolerant approach to mitigate transient and permanent faults of arithmetic and logic operations of embedded processors called FT-EALU is proposed.  ...  Our proposed fault tolerance approach passes the replicated and diverse results to a novel weighted voter that is designed based on the reward/punishment strategy.  ...  Computations are mainly performed in the arithmetic and logic unit (ALU) of the processors so designing them fault-tolerant is very important.  ... 
arXiv:2204.01262v1 fatcat:kwkzgts5vbfchiwk3mh2bgza2e

Session 9 Overview: ML Processors From Cloud to Edge

SukHwan Lim, Luca Benini, Vivienne Sze
2021 2021 IEEE International Solid- State Circuits Conference (ISSCC)  
Their 19.6mm 2 chip demonstrates up to 3.5TFLOPS/W and up to 25.6TFLOPS hybrid fp8 isoaccuracy training, up to 16TOPS/W and 102TOPS int4 inference, as well as support for fp16, fp32 and int2 computation  ...  energy per frame. 7:56 AM A Background-Noise and Process-Variation-Tolerant 109nW Acoustic Feature Extractor Based on Spike-Domain Divisive-Energy Normalization for an Always-On Keyword Spotting Device  ...  and an error-tolerant sequence analyzer for dynamic gesture recognition.  ... 
doi:10.1109/isscc42613.2021.9365814 fatcat:xny3qetafnhrflurtgr22xznzu

Conference Report Fourth Symposium on Computer Arithmetic: Crunching with Quality and LSI

1979 Computer  
As computer applications continue to demand faster computation rates, arithmeticians are seeking, new and more efficient representations of real numbers.  ...  , mathematical software, computer architecture, fault-tolerance, logic design, and IC design  ...  add.  ... 
doi:10.1109/mc.1979.1658706 fatcat:ebvptznev5fkdmfa47t6dfj6y4

Low Power Adaptive Filters Based on a Combination of Genetic Optimization and Residue Number System Coding

C. Radhakrishnan, W. K. Jenkins, D. J. Krusienski
2007 Asilomar Conference on Signals, Systems and Computers. Conference Record  
It is then shown how modular hardware can be designed with residue number system (RNS) coding to provide improved resistance to transient (soft) errors in low power realizations of adaptive filters that  ...  This paper investigates design strategies for achieving reliable performance in low power VLSI adaptive filters that are prone to transient errors due to increasingly smaller feature dimensions and supply  ...  FAULT TOLERANCE BASED ON RNS ARITHMETIC Additional fault tolerance can be introduced into VLSI chip designs through the use of residue number system (RNS) coding.  ... 
doi:10.1109/acssc.2007.4487462 fatcat:4shoq5c7ofhfxbdrgguxfrtxfe

Fixed Point Lanczos: Sustaining TFLOP-equivalent Performance in FPGAs for Scientific Computing

Juan L. Jerez, George A. Constantinides, Eric C. Kerrigan
2012 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines  
If there are several independent problems to solve simultaneously it is possible to exceed the peak floating-point performance of a GPGPU, obtaining approximately 1, 2 or 4 TFLOPs for error tolerances  ...  Current approaches fail to provide tight bounds for this type of algorithms.  ...  arithmetic unit for different number of bits and data representations [20].  ... 
doi:10.1109/fccm.2012.19 dblp:conf/fccm/JerezCK12 fatcat:gm3apegjnfdklhfyhm3axev4eu

Single flux quantum one-decimal-digit RNS adder

Nada Vukovic, Marc J Feldman
1999 APPLIED SUPERCONDUCTIVITY  
AbstractÐResidue number system (RNS) arithmetic has a promising role for fault-tolerant high throughput superconducting single¯ux quantum (SFQ) circuits for digital signal processing (DSP) applications  ...  We have designed one of the basic computational blocks used in DSP circuits, one-decimaldigit RNS adder. A new design for its main component, the single-modulus adder, has been developed.  ...  AcknowledgementsÐThe authors would like to thank Qing Ke for bringing the RNS concept to their attention.  ... 
doi:10.1016/s0964-1807(99)00018-6 fatcat:3oikjjdganevvgmf6noskokj64

Fault Tolerant Digital Data-Path Design via Control Feedback Loops

Oana Boncalo, Alexandru Amaricai, Zsófia Lendek
2020 Electronics  
We apply the proposed methodology on the data-path of a controller designed for a 2-degree of freedom robot arm, and compare the cost and reliability to the generic triple modular redundancy.  ...  Based on the corresponding dynamic model, we design feedback control loops with the goal of attenuating the effect of the faults on the output.  ...  , multiplications, and multiply-add fused.  ... 
doi:10.3390/electronics9101721 fatcat:qcebbayxpnhrzho2ws3zh3567q

A CORDIC-Based Low-Power Statistical Feature Computation Engine for WSN Applications

Dwaipayan Biswas, Koushik Maharatna
2015 Circuits, systems, and signal processing  
Therefore, the design can be applicable for low-power realtime operations within a WSN node.  ...  In this paper we present a carry-save arithmetic (CSA) based Coordinate Rotation Digital Computer (CORDIC) engine for computing eight fundamental time domain statistical features.  ...  For the sake of convenience, we consider 2 squaring units as 1 multiplier, therefore we require 2.5 multipliers in total (1 + 1.5 squaring unit).  ... 
doi:10.1007/s00034-015-0041-5 fatcat:fdllfkwbl5cyxlw5m77l3x2mo4

Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review

Joseph Crop, Evgeni Krimer, Nariman Moezzi-Madani, Robert Pawlowski, Thomas Ruggeri, Patrick Chiang, Mattan Erez
2011 Journal of Low Power Electronics and Applications  
Thus, allowing for an average case oriented design is a promising solution, maintaining the pace of performance improvement over future generations.  ...  One of these challenges is variation, resulting in deviations in the behavior of transistors, most importantly in switching delays.  ...  Acknowledgements This work was funded in part by grants from the Department of Energy Early Career Program, the Center for the Design of Analog-Digital Integrated Circuits, DARPA contract HR0011-10-9-0008  ... 
doi:10.3390/jlpea1030334 fatcat:5hwevwjj2fbzvaeume46u7nuom

Error mitigation in digital logic using a feedback equalization with schmitt trigger (FEST) circuit

Zafar Takhirov, Bobak Nazer, Ajay Joshi
2012 Thirteenth International Symposium on Quality Electronic Design (ISQED)  
This limits the amount of voltage scaling that can be applied for a target performance.  ...  For a 4-bit, 22 nm Kogge-Stone adder designed for 2 GHz operation, the proposed technique lowers the critical voltage (beyond which frequent timing errors occur) from 580 mV (nominal design) to 510 mV  ...  In our considerations, the multiply-accumulate circuits required for DFE far exceed the complexity of the digital arithmetic logic we are trying to protect.  ... 
doi:10.1109/isqed.2012.6187511 dblp:conf/isqed/TakhirovNJ12 fatcat:56heswbu3rfjnjtwd47mxt3bia

Computation Error Analysis in Digital Signal Processing Systems With Overscaled Supply Voltage

Yang Liu, Tong Zhang, Keshab K. Parhi
2010 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Therefore, the selection of appropriate computer arithmetic architecture is an important issue in voltage-overscaled signal processing system design.  ...  Due to the computation-intensive nature of most signal processing algorithms, the energy saving potential largely depends on the behavior of computer arithmetic units in response to overscaled supply voltage  ...  For the search of proper computer arithmetic architecture, we developed an analytical method that could efficiently estimate the computation error statistics of computer arithmetic units under an overscaled  ... 
doi:10.1109/tvlsi.2009.2012863 fatcat:jzh5mntvebcx7crc3wlcvdjufu

Minimum-Energy Operation Via Error Resiliency

Rami A. Abdallah, Naresh R. Shanbhag
2010 IEEE Embedded Systems Letters  
In this letter, we study the impact of error resiliency, in particular algorithmic-noise tolerance (ANT) (Hedge and Shanbhag, IEEE Trans.  ...  We demonstrate a 26% reduction in the total energy of an ANT-based filter in a commercial 130-nm CMOS process along with increased robustness to voltage variations.  ...  This letter studies the impact of ANT on the MEOP of a multiply-add-accumulate (MAC)-based finite-impulse response (FIR) filter.  ... 
doi:10.1109/les.2010.2098330 fatcat:3nvkahy5dbcvpl6urnf3ei6yzq

StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox [chapter]

Oskar Mencer, Heiko Hübert, Martin Morf, Michael J. Flynn
2000 Lecture Notes in Computer Science  
We apply the principles of object-oriented programming to the design of stream architectures for reconfigurable computing.  ...  The StReAm abstraction of PAM-Blox can handle combinational, fully pipelined, and sequential (iterative) arithmetic units.  ...  Wawrzynek, and Arvind for helpful discussions on module-generation and the programming approach to hardware design. Thanks to Compaq Systems Research Center for support of this work, and M.  ... 
doi:10.1007/3-540-44614-1_64 fatcat:i4u2dqlckbfmpadi7leowymv7u
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