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Relocation-Aware Floorplanning for Partially-Reconfigurable FPGA-Based Systems

Marco Rabozzi, Riccardo Cattaneo, Tobias Becker, Wayne Luk, Marco D. Santambrogio
2015 2015 IEEE International Parallel and Distributed Processing Symposium Workshop  
Within this paper we present a floorplanner for partially-reconfigurable FPGAs that allow the designer to consider bitstream relocation constraints during the design of the system.  ...  The presented approach is an extension of our previous work on floorplanning based on a Mixed-Integer Linear Programming (MILP) formulation, thus allowing the designer to optimize a set of different metrics  ...  INTRODUCTION Within the context of floorplanning for partiallyreconfigurable FPGAs [1] , bitstream relocation is the capability of moving a task from an area of the FPGA to another one simply by moving  ... 
doi:10.1109/ipdpsw.2015.52 dblp:conf/ipps/RabozziCBLS15 fatcat:7tczqaa2hrdr7h3i53dogeekly

AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs

Andre Lalevee, Pierre-Henri Horrein, Matthieu Arzel, Michael Hubner, Sandrine Vaton
2016 2016 Euromicro Conference on Digital System Design (DSD)  
Dynamic and partial reconfiguration of Field Programmable Gate Arrays (FPGA) enable to reuse logic resources for several applications which are scheduled in a sequential order or which are loaded on demand  ...  A fraction of the design on the FPGA is then substituted by another logic function while the rest of the system on the chip stays unaffected.  ...  Bitstream relocation on Xilinx FPGAs Bitstream relocation is a technique that allows a partial bitstream to be used to reconfigure a part of the FPGA for which it was not generated.  ... 
doi:10.1109/dsd.2016.92 dblp:conf/dsd/LaleveeHAHV16 fatcat:xcsvijsk3nfodd2pi57bkopvpy

FPGA Dynamic and Partial Reconfiguration

Kizheppatt Vipin, Suhaib A. Fahmy
2018 ACM Computing Surveys  
Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs).  ...  We then investigate design flows, and identify the key challenges in making reconfigurable FPGA systems easier to design.  ...  Again, this assumption does not hold for modern FPGAs. In [Montone et al. 2010] , the authors present a reconfiguration-aware "floorplacer".  ... 
doi:10.1145/3193827 fatcat:tbks3e734zdkdceihncpdeawia

Design of Hardened Embedded Systems on Multi-FPGA Platforms

Cristiana Bolchini, Chiara Sandionigi
2014 ACM Transactions on Design Automation of Electronic Systems  
The aim of this article is the definition of a reliability-aware methodology for the design of embedded systems on multi-FPGA platforms.  ...  Two categories of faults are identified, based on their impact on the device elements; (i) recoverable faults, transient problems that can be fixed without causing a lasting effect namely and (ii) nonrecoverable  ...  Partial dynamic reconfiguration and bitstream relocation provided by Xilinx FPGAs are used for defining online approaches.  ... 
doi:10.1145/2676551 fatcat:atnpvpfcl5eslnvievo3ijjo4a

Go Ahead: A Partial Reconfiguration Framework

Christian Beckhoff, Dirk Koch, Jim Torresen
2012 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines  
In this paper, we introduce the tool GOAHEAD that is able to implement run-time reconfigurable systems for all recent Xilinx FPGAs.  ...  GOAHEAD enables the building of flexible systems for integrating many reconfigurable modules very efficiently into a system.  ...  MODULE RELOCATION AND COMPONENT-BASED DESIGN The capability to isolate modules and to relocate them to different positions on an FPGA is essential for all more advanced reconfigurable systems (or for a  ... 
doi:10.1109/fccm.2012.17 dblp:conf/fccm/BeckhoffKT12 fatcat:zgry7hjcm5dj7mt3oob2eqdbmy

Hierarchical reconfiguration of FPGAs

Dirk Koch, Christian Beckhoff
2014 2014 24th International Conference on Field Programmable Logic and Applications (FPL)  
Partial reconfiguration allows some applications to substantially save FPGA area by time sharing resources among multiple modules.  ...  This is useful for complex systems where many modules have common parts or where modules can share components.  ...  Note that more than two levels of partial reconfiguration might be used for large FPGAs.  ... 
doi:10.1109/fpl.2014.6927491 dblp:conf/fpl/KochB14 fatcat:t2q2jjhlgna5zbo7nqgn3vkipq

Design space exploration for partially reconfigurable architectures in real-time systems

François Duhem, Fabrice Muller, Willy Aubry, Bertrand Le Gal, Daniel Négru, Philippe Lorenzini
2013 Journal of systems architecture  
The flow is based upon our SystemC simulator for real-time systems that helps develop and validate scheduling algorithms with respect to application timing constraints and partial reconfiguration physical  ...  In this paper, we introduce FoRTReSS (Flow for Reconfigurable archiTectures in Real-time SystemS), a methodology for the generation of partially reconfigurable architectures with real-time constraints,  ...  dynamic and partial reconfiguration.  ... 
doi:10.1016/j.sysarc.2013.06.007 fatcat:dixe4ecqyrce7prltrqkvrxaze

IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs

Khoa Pham, Edson Horta, Dirk Koch, Anuj Vaishnav, Thomas Kuhn
2018 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)  
Systems designed by the proposed IPRDF are not only fully isolated but also support partial reconfiguration of insulated modules.  ...  This allows building secure and dependable systems that can use partial reconfiguration to mitigate from single-event upsets (SEUs) and that are more tolerant to aging and device imperfections.  ...  System Implementation We have revised the Floorplan for the Xilinx IDF reference to reserve two partially reconfigurable regions for Keccak cryptographic modules.  ... 
doi:10.1109/mcsoc2018.2018.00018 dblp:conf/mcsoc/PhamHKVK18 fatcat:dlxpbrpxtnf3lpnq2cngboxccq

Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC

Biruk B. Seyoum, Marco Pagani, Alessandro Biondi, Giorgio C. Buttazzo
2021 ACM Symposium on Applied Computing  
The tool targets the Zynq 7-series and Ultrascale+ FPGA-based SoCs by Xilinx.  ...  Despite its benefits, hardware acceleration under dynamic partial reconfiguration (DPR) has not been fully leveraged by many system designers, mostly due to the complexities of the DPR design flow and  ...  Furthermore, the dynamic partial reconfiguration (DPR) capabilities of modern FPGA-based SoC platforms can be leveraged to improve resource utilization, resulting in lower requirements in terms of FPGA  ... 
doi:10.1145/3412841.3441928 dblp:conf/sac/SeyoumPBB21 fatcat:fwfcfq276vgsjowgqbftkeabvy

Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms

Cristiana Bolchini, Antonio Miele, Chiara Sandionigi
2013 Journal of electronic testing  
This paper presents an approach for increasing the lifetime of systems implemented on SRAM-based FPGAs, by introducing fault tolerance properties enabling the system to autonomously manage the occurrence  ...  On the basis of the foreseen mission time and application environment, the designer is supported in the implementation of a system able to reconfigure itself, either by reloading the correct configuration  ...  The T3RSS project [20] proposes a tool for a systematic approach to design hardened systems hosted on SRAMbased FPGAs, by means of relocation and reconfiguration.  ... 
doi:10.1007/s10836-013-5418-4 fatcat:uerkb6tpozhpdc4tp3ibs5i5gy

Efficient Interfacing of Partially Reconfigurable Instruction Set Extensions for Softcore CPUs on FPGAs

Dirk Koch, Christian Beckhoff, Jim Torresen
2011 Journal of Integrated Circuits and Systems  
For removing this overhead, we propose a novel technique to constrain the communication resources between the static system and the partial regions.We will demonstrate for a reconfigurable soft core processor  ...  In this paper, we will sketch that present design techniques include a substantial overhead for integrating reconfigurable parts into the rest of the system.  ...  When floorplanning a reconfigurable system, it is recommended to consider the underlying FPGA architecture.  ... 
doi:10.29292/jics.v6i1.336 fatcat:b5bmdbgfifdwtesdlo3akkgaqi

Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems [article]

Daniel Ziener
2018 arXiv   pre-print
In this treatise, my research on methods to improve efficiency, reliability, and security of reconfigurable hardware systems, i.e., FPGAs, through partial dynamic reconfiguration is outlined.  ...  In the area of reliability, countermeasures against radiation-induced faults and aging effects for long mission times were investigated and applied to SRAM-FPGA-based satellite systems.  ...  The research has been carried out in collaboration with several doctoral researchers, master and bachelor students from my research group Reconfigurable Computing. In  ... 
arXiv:1809.11156v1 fatcat:6ttulp2tancyvds7fk2coxoptq

Component based design using constraint programming for module placement on FPGAs

Alexander Wold, Dirk Koch, Jim Torresen
2013 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)  
In this paper, we present a constraint solver targeting module placement in static and partial run-time reconfigurable systems. We use the constraint solver to compute feasible placement positions.  ...  Our work targets state of the art field-programmable gate arrays (FPGAs) in both design-time and run-time applications.  ...  ACKNOWLEDGMENT This work is funded by THE RESEARCH COUNCIL OF NORWAY as part of the Context Switching Reconfigurable Hardware for Communication Systems (COSRECOS) [30] project, under grant 191156V30.  ... 
doi:10.1109/recosoc.2013.6581541 dblp:conf/recosoc/WoldKT13 fatcat:q43yc2unkbba3jvxlju3dybzem

An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable Systems

A. Al-Wattar, S. Areibi, G. Grewal
2016 International Journal of Reconfigurable Computing  
A supporting framework for efficient mapping of execution units to task graphs in a run-time reconfigurable system is also designed.  ...  Several embedded application domains for reconfigurable systems tend to combine frequent changes with high performance demands of their workloads such as image processing, wearable computing, and network  ...  task graphs for partial dynamic reconfigurable systems.  ... 
doi:10.1155/2016/9012909 fatcat:qqds25ixejhejge5zmarasllxa

Hardware Task Scheduling for Partially Reconfigurable FPGAs [chapter]

George Charitopoulos, Iosif Koidis, Kyprianos Papadimitriou, Dionisios Pnevmatikatos
2015 Lecture Notes in Computer Science  
reconfigurable regions of a partially reconfigurable FPGA.  ...  Partial reconfiguration (PR) of FPGAs can dynamically extend and adapt the functionality of computing systems by swapping in and out HW tasks.  ...  As listed above, many researchers have proposed and created scheduling algorithms, placement algorithms, for managing hardware tasks on a partially reconfigurable FPGA based operating system, and complete  ... 
doi:10.1007/978-3-319-16214-0_45 fatcat:jhc6hro67bdb3of6eenubufkmi
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