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Front Matter: Volume 8522

Proceedings of SPIE, Frank E. Abboud, Thomas B. Faure
2012 Photomask Technology 2012  
The CID Number appears on each page of the manuscript. The complete citation is used on the first page, and an abbreviated version on subsequent pages.  ...  The papers included in this volume were part of the technical conference cited on the cover and title page. Papers were selected and subject to review by the editors and conference program committee.  ...  Patil, SoftJin Technologies Pvt. Ltd. (India) 8522 1Z RDMS: a Windows and tablet PC based reticle defect search database with AHDC for interconnected mask and wafer fabs [8522-71] S. Munir, G.  ... 
doi:10.1117/12.2008671 fatcat:kdx6hezvqrd4xjz7l7f5ohmgru

Front Matter: Volume 8552

Ning Hua Zhu, Jinmin Li, Frank H. Peters, Changyuan Yu
2012 Semiconductor Lasers and Applications V  
The CID Number appears on each page of the manuscript. The complete citation is used on the first page, and an abbreviated version on subsequent pages.  ...  The papers included in this volume were part of the technical conference cited on the cover and title page. Papers were selected and subject to review by the editors and conference program committee.  ...  Patil, SoftJin Technologies Pvt. Ltd. (India) 8522 1Z RDMS: a Windows and tablet PC based reticle defect search database with AHDC for interconnected mask and wafer fabs [8522-71] S. Munir, G.  ... 
doi:10.1117/12.1518468 fatcat:f3k4movpo5cyzihij57xp3bpfy

Table of Contents

2021 2021 IEEE International Interconnect Technology Conference (IITC)  
Invited Speech: On-die interconnect technologies for future technology nodes Mauro Kobrinsky Intel 11:00 am -11:30 am S8-2.  ...  Metal Wet Recess Challenges and Solutions for Beyond 7nm Fully Aligned via Integration Corneliu Brown Peethala{1}, Devika Sil{1}, Benjamin Briggs{1}, David Rath{1}, Nick Lanzillo{1}, Kedari Matam{1}, Hosadurga  ... 
doi:10.1109/iitc51362.2021.9537562 fatcat:weqz7hy4svah5hwuhdd5iflkcu

State-of-the-Art and Trends for Computing and Interconnect Network Solutions for HPC and AI

A. Tekin, A.Tuncer Durak, C. Piechurski, D. Kaliszan, F. Aylin Sungur, F. Robertsén, P. Gschwandtner
2021 Zenodo  
The present report provides a consolidated view on the current and mid-term technologies (2019-2022+) for two important components of an HPC/AI system: computing (general purpose processor and accelerators  ...  ) and interconnect capabilities and provides an outlook on future trends in terms of mid-term projections about what users may expect in the coming years.  ...  Acknowledgements This work was financially supported by the PRACE project funded in part by the EU's Horizon 2020 Research and Innovation programme (2014-2020) under grant agreement 823767.  ... 
doi:10.5281/zenodo.5717283 fatcat:irgzrdxr6ncijcfxsdb3sdodii

State-of-the-Art and Trends for Computing and Interconnect Network Solutions for HPC and AI

A. Tekin, A.Tuncer Durak, C. Piechurski, D. Kaliszan, F. Aylin Sungur, F. Robertsén, P. Gschwandtner
2021 Zenodo  
The present report provides a consolidated view on the current and mid-term technologies (2019-2022+) for two important components of an HPC/AI system: computing (general purpose processor and accelerators  ...  ) and interconnect capabilities and provides an outlook on future trends in terms of mid-term projections about what users may expect in the coming years.  ...  Acknowledgements This work was financially supported by the PRACE project funded in part by the EU's Horizon 2020 Research and Innovation programme (2014-2020) under grant agreement 823767.  ... 
doi:10.5281/zenodo.5534079 fatcat:fdknu7w4mfc5foa4gnmt5vqdna

Design for manufacturability and reliability in extreme-scaling VLSI

Bei Yu, Xiaoqing Xu, Subhendu Roy, Yibo Lin, Jiaojiao Ou, David Z. Pan
2016 Science China Information Sciences  
Keywords design for manufacturability, design for reliability, VLSI CAD Citation Yu B, Xu X Q, Roy S, et al. Design for manufacturability and reliability in extreme-scaling VLSI.  ...  and targeting for research and development.  ...  The authors would like to thank Meng LI and Wei YE at University of Texas for helpful comments. Conflict of interest The authors declare that they have no conflict of interest.  ... 
doi:10.1007/s11432-016-5560-6 fatcat:lz5ebjqeprbanbkgxqxjeouip4

Performace modeling and optimization for on-chip interconnects in memory arrays

Javaneh Mohseni, Chenyun Pan, Azad Naeemi
2015 2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)  
beyond-2020 technology generations.  ...  Using 111 In addition to the the memory and interconnect technologies covered in this work, some of the emerging device and interconnect technologies pursued in order to extend Moore's law to beyond  ... 
doi:10.1109/epeps.2015.7347150 fatcat:wlqdssnf7vbhzilesre4rzybba

Future HPC Technologies

Jean-François Lavignon
2020 Zenodo  
The three main HPC ecosystems beside Europe, namely US, China and Japan have undertaken significant research initiatives to work on these new approaches.  ...  The last section presents some recommendations for Europe to strengthen its position in technologies relevant for future HPC system.  ...  Extreme ultraviolet lithography -EUV or EUVL), and the power density of those technologies is still not known, perhaps limiting the number of devices active at the same moment on the die.  ... 
doi:10.5281/zenodo.4106742 fatcat:ybxhgen7nzet7i7bubwou2u55a

D3.4 Intermediate COREnect Industry Roadmap [article]

AUSTRALO
2022 Zenodo  
One of the key COREnect objectives is to define a strategic R&I roadmap for future European connectivity systems and components, supporting Europe's strategic autonomy and sovereignty objectives.  ...  This roadmap is being defined based on input from all relevant stakeholders across different domains and communities (including SNS and KDT), covering the relevant actors from industry, research, academia  ...  Similarly, the technology used by ASML for its flagship EUV lithography started in the 1980s on the use of soft x-rays.  ... 
doi:10.5281/zenodo.5863480 fatcat:fvr57ujos5f2la2trwdtfurlb4

Eurolab-4-HPC Long-Term Vision on High-Performance Computing [article]

Theo Ungerer, Paul Carpenter
2018 arXiv   pre-print
Because of the long-term perspective and its speculative nature, the authors started with an assessment of future computing technologies that could influence HPC hardware and software.  ...  The proposal on research topics is derived from the report and discussions within the road mapping expert group.  ...  GlobalFoundries Updates Roadmap: 7 nm in 2H 2018, EUV Sooner Than Later?: http://www.anandtech.com/ show/10704/globalfoundries-updates-roadmap-7nm-in-2h-2018. [ 9 ] 9 N. Hemsoth.  ... 
arXiv:1807.04521v1 fatcat:5neetrgubjhnvcajcktpkohrzq

COREnect D3.3. Initial COREnect industry roadmap [article]

AUSTRALO
2021 Zenodo  
Similarly, the technology used by ASML for its flagship EUV lithography started in the 1980s on the use of soft x-rays.  ...  intruding into this market for 5G and beyond looks very difficult on the short and midterm.  ...  Appendix The COREnect roadmap activities strongly rely on interactions with experts in the field.  ... 
doi:10.5281/zenodo.5075317 fatcat:ww7icphzfjcdjlxbsbo2qekghy

Panel: Looking Backwards and Forwards

Marco Casale-Rossi, Giovanni De Micheli, Antun Domic, Enrico Macii, Domenico Rossi, Joe Sawicki
2016 Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)   unpublished
What is EDA doing and, more important, what should EDA do -and is not doing -in order for the next decade to be as great as the past one?  ...  Also thanks to EDA, tools, methodologies, and flows that were originally devised for design enablement for the emerging technology nodes, have been successfully redeployed at the established technology  ...  On the technical side, we are already deep into the development phase for 7nm and can see a reasonable path to 5nm. The need is there.  ... 
doi:10.3850/9783981537079_0976 fatcat:ftim4buq2fdffdnav7za7ap57q

Scaling Moore's Wall: Existing Institutions and the End of a Technology Paradigm

Hassan Khan
2018
This study first provides theoretical and historical context for the phenomenon under consideration.  ...  For nearly 60 years, semiconductor technology has been defined by rapid rates of progress and concomitant decreases in costs-perfunction made possible by the extendibility of the silicon integrated-circuit  ...  Acknowledgements The journey to completing and submitting a dissertation has been far different than what I originally envisioned.  ... 
doi:10.1184/r1/6721397.v1 fatcat:iorsmrvbkfaspjghhqvcojwo5q

Metallic nanotransistors [article]

Han-Hao Cheng, University Of Canterbury
2009
In the fabrication, the minimum achievable line widths is mainly determined by the surface charging effects due to the direct EBL patterning on insulating substrates and by proximity effects for having  ...  Metallic nanowire devices were deposited on insulating substrates such as Si₃N₄ or SiO₂ to facilitate electrical characterisation and device operation.  ...  , extreme ultraviolet lithography [30] (EUV), and multiple beam lithography [31] .  ... 
doi:10.26021/2433 fatcat:5dsw76iz5zbqzlvtbwdzmblfjm

an ion beam complement to electron beam writers

Lars Bruchhaus, Technische Universität Dortmund, Technische Universität Dortmund
2012
In our experiments we have exploited also additional ion-matter interactions to the two current main stream ones (sputtering and gas assisted processing).  ...  For example employing 40 keV Ga ions, we have analysed two applications in more detail: We exposed a 6 nm thin hydrogen silsesquioxane (HSQ) resist and reached a line-width thinner than 10 nm as well as  ...  However, the future of focused ion beam technology in nano patterning will depend on profound theory beyond conventional analysis and micro patterning applications.  ... 
doi:10.17877/de290r-14294 fatcat:cugxlek5xrhjvg65uuwpnzk2m4
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