Filters








15,800 Hits in 6.6 sec

Reliability evaluation of logic circuits based on transient faults propagation metrics

Shuo Cai, Fei Yu, Weizheng Wang, Tieqiao Liu, Peng Liu, Wei Wang
2017 IEICE Electronics Express  
Using these faults propagation features, the reliability of combinational circuits and full scan sequential circuits are evaluated efficiently.  ...  This paper proposes a reliability evaluation approach for logic circuits based on transient faults propagation metrics (TFPMs).  ...  Reliability evaluation of logic circuits The reliability of a combinational circuit is defined as the probability of the primary outputs with expected logic values.  ... 
doi:10.1587/elex.14.20170128 fatcat:wqi77otwnbgnjigme5somofz2a

Analysis of combinational networks with mathematics

Dejan Tosic, Slobodan Simic
2005 Publikacija Elektrotehnickog fakulteta - serija matematika  
The symbolic analysis addressed in this work can serve as a basis of efficient programs for variety of logic design tasks, including logic simulation, fault simulation, test generation, and symbolic verification  ...  A novel program is presented to carry out the symbolic analysis, and to derive closed-form formulas for the response of combinational networks, for excitations specified by symbols or symbolic expressions  ...  Fully automated computer-aided symbolic analysis of combinational networks has been addressed; it is important for variety of logic design tasks, including logic simulation, fault simulation, test generation  ... 
doi:10.2298/petf0516098t fatcat:p6cexp5eana2naknzxqyo4ys3y

Coded time-symbolic simulation using shared binary decision diagram

Nagisa Ishiura, Yutaka Deguchi, Shuzo Yajima
1990 Conference proceedings on 27th ACM/IEEE design automation conference - DAC '90  
We encode the cases of possible delay values of each gate by binary values and simulate all the possible combinations of the delay values by means of symbolic simulation.  ...  This simulation technique can deal with logic circuits containing feedback loops as well as combinational circuits.  ...  We would like to express our sincere appreciation to the members of Yajima Laboratory a t Kyoto University for their valuable discussions and comments.  ... 
doi:10.1145/123186.123240 dblp:conf/dac/IshiuraDY90 fatcat:cppu6giz6vczlnx7uepdvg7rny

System Reliability Evaluation Method Considering Physical Dependency with FMT and BDD Analytical Algorithm

Ying Chen, Yanfang Wang, Song Yang, Rui Kang
2022 Journal of Systems Engineering and Electronics  
Results show that the method is effective to evaluate system reliability from the perspective of FM.  ...  , and parameter combination.  ...  The CDF of the system can be obtained by combining the logical relationships of components. In our previous study, the Monte Carlo simulation method is used to solve FMT [19−24] .  ... 
doi:10.23919/jsee.2022.000022 fatcat:gtxxbaordfeklgyuprhdwaxb44

Formal modeling and reasoning for reliability analysis

Natasa Miskov-Zivanov, Diana Marculescu
2010 Proceedings of the 47th Design Automation Conference on - DAC '10  
Transient faults in logic circuits are an important reliability concern for future technology nodes.  ...  In order to guide the design process and the choice of circuit optimization techniques, it is important to accurately and efficiently model transient faults and their propagation through logic circuits  ...  In [23] , custom designed circuits were simulated using HSPICE. The benchmark circuits considered by the authors were analyzed by running separate simulations for each discrete parameter value.  ... 
doi:10.1145/1837274.1837406 dblp:conf/dac/Miskov-ZivanovM10 fatcat:qroy4m4nerha5lqehhhb4a3rii

MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits

Natasa Miskov-Zivanov, Diana Marculescu
2007 8th International Symposium on Quality Electronic Design (ISQED'07)  
In this paper, we use a symbolic framework based on BDDs and ADDs that enables analysis of sequential circuit reliability from different aspects: output susceptibility to error, influence of individual  ...  gates on individual outputs and overall circuit reliability, and the dependence of circuit reliability on glitch duration, amplitude, and input patterns.  ...  Most of the previous work in evaluating SER in sequential circuits has been done using simulation. Similar to combinational circuits, the alternative to simulation is analytical/symbolic modeling.  ... 
doi:10.1109/isqed.2007.100 dblp:conf/isqed/Miskov-ZivanovM07 fatcat:piwym5vwkzc6zeosth5chwmgyq

Formal reliability analysis of combinational circuits using theorem proving

Osman Hasan, Jigar Patel, Sofiène Tahar
2011 Journal of Applied Logic  
Traditionally, reliability analysis of combinational circuits is done using simulation or paper-and-pencil proof methods.  ...  We present the higher-order-logic formalization of the notions of fault and reliability for combinational circuits and formally verify the von-Neumann fault models for most of the commonly used logic gates  ...  This means that the probability of obtaining a logical 1 for a combinational circuit with erroneous gates can be evaluated based on these theorems by simple rewriting.  ... 
doi:10.1016/j.jal.2011.01.002 fatcat:xx4cpiunkjd35fd4hfa3mmbkd4

Validating PowerPC microprocessor custom memories

N. Krishnamurthy, A.K. Martin, M.S. Abadir, J.A. Abraham
2000 IEEE Design & Test of Computers  
Address Data in Read enable Write enable C1 clock Data in Read/write control logic Address decode logic Data conditioning logic Sense-amp outputs column MUX Figure 15. Custom memory.  ...  Acknowledgments We thank the entire project and tools teams at Somerset, Motorola, for their cooperation and commitment to the successful conclusion of this project.  ...  Symbolic trajectory evaluation (STE) is a modified form of symbolic simulation that operates over the quaternary logic domain 0, 1, X, and ‫.ׅ‬ 13, 14 A state of the circuit is defined as the set of  ... 
doi:10.1109/54.895007 fatcat:t3w2vughyzem5ot2okcxnb43hm

Gate-Level Circuit Reliability Analysis: A Survey

Ran Xiao, Chunhong Chen
2014 VLSI design (Print)  
While quite a few approaches for circuit reliability analysis have been reported, there is a lack of comparative studies on their pros and cons in terms of both accuracy and efficiency.  ...  This paper provides an overview of some typical methods for reliability analysis with focus on gate-level circuits, large or small, with or without reconvergent fanouts.  ...  Conflict of Interests The authors declare that there is no conflict of interests regarding the publication of this paper.  ... 
doi:10.1155/2014/529392 fatcat:vwersghvkbglxoajmew2cw7vcm

Circuit Reliability Analysis Using Symbolic Techniques

Natasa Miskov-Zivanov, Diana Marculescu
2006 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
To estimate the susceptibility to errors in combinational logic, we propose the use of Binary Decision Diagrams (BDDs) and Algebraic Decision Diagrams (ADDs) for unified symbolic analysis of circuit reliability  ...  We present a framework that uses BDDs and ADDs and enables analysis of combinational circuits reliability from different aspects: output susceptibility to error, influence of individual gates on individual  ...  Our main goal is to allow for symbolic modeling and efficient estimation of the soft error susceptibility of a combinational logic circuit.  ... 
doi:10.1109/tcad.2006.882592 fatcat:pvyj7hb2c5az7k6azpp27c66nu

Exact stuck-at fault classification in presence of unknowns

Stefan Hillebrecht, Michael A. Kochte, Hans-Joachim Wunderlich, Bernd Becker
2012 2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS)  
The accuracy of the computation of fault coverage in classic n-valued simulation algorithms is compromised by unknown (X) values.  ...  The applicability of our algorithm to large industrial circuits is demonstrated.  ...  This work was partially supported by the German Research Foundation (DFG) under grants BE 1176/14-2 and WU 245/5-2.  ... 
doi:10.1109/ets.2012.6233017 dblp:conf/ets/HillebrechtKWB12 fatcat:usqwse64ubf3tkxn6g47yd2ooy

Soft Error Rate Analysis for Sequential Circuits

Natasa Miskov-Zivanov, Diana Marculescu
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
The results obtained with the proposed symbolic framework are within 4% average error and up to 11000X faster when compared to HSPICE detailed circuit simulation.  ...  The SER evaluation is demonstrated by the set of experimental results, which show that, for most of the benchmarks used, the SER decreases well below a given threshold (10 -7 FIT) within ten clock cycles  ...  Symbolic modeling vs. simulation We use HSPICE simulation to evaluate the accuracy of the results we obtain using approximate symbolic model of the circuit.  ... 
doi:10.1109/date.2007.364500 fatcat:qy743fbs4jcufd7pye7a7xltva

Signature-Based SER Analysis and Design of Logic Circuits

Smita Krishnaswamy, Stephen M. Plaza, Igor L. Markov, John P. Hayes
2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In the second part of the paper, we incorporate AnSER into logic synthesis design flows aimed at reliable circuit design.  ...  Consequently, AnSER evaluates logic masking two to three orders of magnitude faster than other SER evaluators while maintaining accuracy.  ...  AnSER, our technologyindependent SER analyzer, accurately evaluates the logic masking in combinational and sequential logic circuits.  ... 
doi:10.1109/tcad.2008.2009139 fatcat:a6g4gyx6drdwheewfp2tjac7zq

Hazard detection by a quinary simulation of logic devices with bounded propagation delays

Daniel W. Lewis
1972 Proceedings of the ninth design automation workshop on Design automation - DAC '72  
Effective logic simulation programs must consider device propagation delays to be bounded values. This requires that the logic devices be simulated by models which use a multi-valued logical algebra.  ...  A quinary algebra is developed and employed in special algorithms which not only accurately predict the behavior of a logic circuit for all values of delay, but also detect the possibility of latent hazards  ...  Basically, the problem lies in the fact that the simulation models of the logic devices have not been complete enough to reliably predict the behavior of a circuit for all combinations of device delays  ... 
doi:10.1145/800153.804941 dblp:conf/dac/Lewis72 fatcat:kbblbn3c6jgsdlfe422hkldc3y

MARS-C: modeling and reduction of soft errors in combinational circuits

N. Miskov-Zivanov, D. Marculescu
2006 Proceedings - Design Automation Conference  
In this paper, we present a symbolic framework based on BDDs and ADDs that enables analysis of combinational circuit reliability from different aspects: output susceptibility to error, influence of individual  ...  gates on individual outputs and overall circuit reliability, and the dependence of circuit reliability on glitch duration, amplitude, and input patterns.  ...  Our main goal is to allow for symbolic modeling and efficient estimation of the susceptibility of a combinational logic circuit to soft errors.  ... 
doi:10.1109/dac.2006.229323 fatcat:mbehz4zi2fajtiekda4dzzf6gq
« Previous Showing results 1 — 15 out of 15,800 results