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Production scheduling in a semiconductor wafer fabrication facility producing multiple product types with distinct due dates

Yeong-Dae Kim, Jae-Gon Kim, Bum Choi, Hyung-Un Kim
2001 IEEE Transactions on Robotics and Automation  
What need to be done for production scheduling are lot release control (to determine when and which wafer lot to release into the wafer fab), lot scheduling (to determine processing sequences of lots waiting  ...  In the wafer fab, wafer lots are processed on serial and batch processing workstations, each of which consists of parallel identical machines.  ...  What need to be done for production scheduling are lot release control (to determine when and which wafer lot to release into the wafer fab), lot scheduling (to determine processing sequences of lots waiting  ... 
doi:10.1109/70.964660 fatcat:2t2njanenrhhnbce2hz77coypq

Due-date based scheduling and control policies in a multiproduct semiconductor wafer fabrication facility

Yeong-Dae Kim, Jung-Ug Kim, Seung-Kil Lim, Hong-Bae Jun
1998 IEEE transactions on semiconductor manufacturing  
This paper focuses on lot release control and scheduling problems in a semiconductor wafer fab producing multiple products that have different due dates and different process flows.  ...  For lot release control, it is necessary to determine the type of a wafer lot and the time to release wafers into the wafer fab, while it is necessary to determine sequences of processing waiting lots  ...  LOT RELEASE CONTROL AND SCHEDULING In this research, two decision problems are considered for production control of a wafer fab, which are lot release (or input) control into the wafer fab and lot scheduling  ... 
doi:10.1109/66.661295 fatcat:rbz2vqtpojaw5awto2r4ygotu4

The Optimal Decision Combination in Semiconductor Manufacturing

Sungwook Yoon, Jihyun Kim, Sukjae Jeong
2017 Sustainability  
In this research, we propose the optimal combination rules for lot scheduling problems in wafer fabs, focusing on three complex areas of decision making: lot release control, batch sizing, and dispatching  ...  In a wafer fabrication facility (fab), wafers are grouped as a lot to go through repeated sequences of operations to build circuitry.  ...  Lot Release in the Wafer Fab Line Lot release control is defined as the decision of the optimal release time into the production line and the release conditions.  ... 
doi:10.3390/su9101788 fatcat:hdamqf7amzdepkvabxpyzzldli

Multi-product lot merging/splitting algorithms for a semiconductor wafer fabrication

June-Young Bang, Jae-Hun Kang, Bong-Kyun Kim, Yeong-Dae Kim
2008 2008 Winter Simulation Conference  
In the fab, two or more lots can be merged into a single lot if routes and all the processing conditions of the lots are the same for a number of subsequent operations, and the merged lot is split into  ...  This paper focuses on a lot merging/splitting problem in a semiconductor wafer fabrication facility.  ...  Kim et al. (1998b Kim et al. ( , 2001 suggest dispatching-rule-based algorithms for lot release control and lot scheduling, and Kim et al. (2003) develop a real-time scheduling method in a wafer fab  ... 
doi:10.1109/wsc.2008.4736321 dblp:conf/wsc/BangKKK08 fatcat:aghnrv6ch5cfnjibzsy6nfhk3e

A Due-Date-Based Algorithm for Lot-Order Assignment in a Semiconductor Wafer Fabrication Facility

Yeong-Dae Kim, June-Young Bang, Kwee-Yeon An, Seung-Kil Lim
2008 IEEE transactions on semiconductor manufacturing  
Index Terms-Lot-order assignment, scheduling, semiconductor wafer fab.  ...  This paper focuses on a lot-order assignment problem, called the pegging problem, in a semiconductor wafer fabrication facility. Pegging is a process of assigning wafer lots to orders for wafers.  ...  Also, in UNIF, a selected lot is released into the fab in a constant rate (up to 3000 wafers a day) regardless of the current systems states.  ... 
doi:10.1109/tsm.2008.2000261 fatcat:vnqpaoifhvf6hny3gw4pcagvhe

Effective Scheduling Of Semiconductor Manufacturing Using Simulation

Ingy A. El-Khouly, Khaled S. El-Kilany, Aziz E. El-Sayed
2011 Zenodo  
Results of simulation showed that the performance of the Mini-Fab can be drastically improved using a combination of dispatching rules and lot release policy.  ...  A number of scenarios have been developed and have been used to evaluate the effect of different dispatching rules and lot release policies on the selected performance measures.  ...  Scheduling Policy For lot release control, it is necessary to select a wafer lot to be released into the fab and to determine the time to release the wafer lot, while it is necessary for lot scheduling  ... 
doi:10.5281/zenodo.1075364 fatcat:c65yeppsg5cwlgihlxvx6sewiy

Daily scheduling for R&D semiconductor fabrication

Da-Yin Liao, Shi-Chung Chang, Kuo-Wei Pei, Chi-Ming Chang
1996 IEEE transactions on semiconductor manufacturing  
for each photolithography operation, loop test and engineering splitting and merging of wafer lots.  ...  Abstruct-This paper presents the development of a daily scheduling tool, Electronic Research & Service Organization Fab Scheduler (ERSOFS), for a research and development (R&D) pilot line of semiconductor  ...  Major production control issues in an IC fab include 1) wafer release of raw wafers into the fab, 2) daily scheduling, and 3 ) lot dispatching to determine which lot to process when a machine becomes available  ... 
doi:10.1109/66.542170 fatcat:6l4pg6aptjfizafllq2ghe2rg4

Simplification methods for accelerating simulation-based real-time scheduling in a semiconductor wafer fabrication facility

Yeong-Dae Kim, Sang-Oh Shim, Bum Choi, Hark Hwang
2003 IEEE transactions on semiconductor manufacturing  
This paper presents a real-time scheduling methodology in a semiconductor wafer fab that produces multiple product types with different due dates.  ...  In the suggested real-time scheduling method, lot scheduling rules and batch scheduling rules are selected from sets of candidate rules based on information obtained from discrete event simulation.  ...  However, since lot release control may be very important in some wafer fabs, lot release control may have to be considered simultaneously with lot and batch scheduling. received August 10, 2001; revised  ... 
doi:10.1109/tsm.2003.811890 fatcat:dt7b267ugjfpfcgkwptozbmqty

Simulation-Based Modular Scheduling System of Semiconductor Manufacturing [chapter]

Li Li, Qiao Fei Ma Yumin, Ye Kai
2012 Production Scheduling  
In view of its process flow, a job will be processed as soon as it is released to a wafer fab.  ...  Modular means that SMSS integrates various kinds of scheduling in a wafer fab, such as release control, sequencing, dynamic dispatching and rescheduling methods.  ...  More specifically, as a part of a larger planning and scheduling process, production scheduling is essential for the proper functioning of a manufacturing enterprise.  ... 
doi:10.5772/26257 fatcat:7u5fotsx3feb3lh3i7eup4jt3m

Efficient scheduling policies to reduce mean and variance of cycle-time in semiconductor manufacturing plants

S.C.H. Lu, D. Ramaswamy, P.R. Kumar
1994 IEEE transactions on semiconductor manufacturing  
Major fab scheduling problems include how wafers should be released into a fab and how they should be dispatched among machines for processing.  ...  A popular practitioners' approach for scheduling the production in a fab is to select from the many empirical scheduling rules available for IC fabs.  ...  In this paper, we adopt the OO-based simulation tool to study dynamic selection of scheduling rules for wafer fab operations.  ... 
doi:10.1109/66.311341 fatcat:o32fmjvhzvbm3nze2rcvpqh4hu

Petri-net and GA-based approach to modeling, scheduling, and performance evaluation for wafer fabrication

Jyh-Horn Chen, Li-Chen Fu, Ming-Hung Lin, An-Chih Huang
2001 IEEE Transactions on Robotics and Automation  
The chromosome representation of the search nodes in GA is constructed directly from the CTPN model, recording the information about the appropriate scheduling policy for each workstation in the fab.  ...  A better chromosome found by GA is received by the CTPN based schedule builder, and then a near-optimal schedule is generated.  ...  The architecture of the scheduler was shown in Fig. 7 , in which, we first select a lot release policy to control the timing for release of a lot (token) to the CTPN model.  ... 
doi:10.1109/70.964663 fatcat:fviq4mefo5h4jf4eobccnzcmt4

A Multiagent-Based Decision-Making System for Semiconductor Wafer Fabrication With Hard Temporal Constraints

Hyun Joong Yoon, Weiming Shen
2008 IEEE transactions on semiconductor manufacturing  
A dynamic planning-based approach is adopted for the decision making mechanism so that the dynamic behaviors of the wafer fab such as aperiodic lot arrivals and reconfiguration can be taken into consideration  ...  Existing approaches to scheduling of wafer fabs with temporal constraints generally focus on development of scheduling methods to meet due dates of orders or wafers.  ...  A lot in a wafer fab implies a cassette or a FOUP (Front Opening Unified Pod) that is a container of wafers for efficient delivery.  ... 
doi:10.1109/tsm.2007.914388 fatcat:lr2svh3f5vd5rp7ihm3ywcqmoy

Scheduling semiconductor wafer fabrication

L.M. Wein
1988 IEEE transactions on semiconductor manufacturing  
A variety of input control and sequencing rules are evaluated using a simulation model of a representative but fictitious semiconductor wafer fab.  ...  The effects that specific sequencing rules have are highly dependent upon both the type of input control used and the number of bottleneck stations in the fab.  ...  When the number of lots in the fab drops to N-1, release a new lot into the fab.  ... 
doi:10.1109/66.4384 fatcat:o7zxgcsfjjapzhcsqm26sveyye

Dynamic Release Control Policy for the Semiconductor Wafer Fabrication Lines

Jongsoo Kim, Robert C. Leachman, Byungkyoo Suh
1996 Journal of the Operational Research Society  
But the scheduling of a wafer fab is challenging due to the long flow time, ever-changing yield of products, re-entrant feature of the production sequence, and stochastic aspects of the wafer fab including  ...  The production of IC’s is accomplished in a four-stage process, namely wafer fabrication (fab), wafer probe, device assembly, and device test.  ... 
doi:10.1057/jors.1996.195 fatcat:nvs2r7tpnjbp3ktcu3kwlmvbei

Scheduling semiconductor wafer fabrication

1989 Microelectronics and reliability  
A variety of input control and sequencing rules are evaluated using a simulation model of a representative but fictitious semiconductor wafer fab.  ...  The effects that specific sequencing rules have are highly dependent upon both the type of input control used and the number of bottleneck stations in the fab.  ...  When the number of lots in the fab drops to N-1, release a new lot into the fab.  ... 
doi:10.1016/0026-2714(89)90263-1 fatcat:s6csqs5q2vhfxhnnhv7w2ywo6m
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