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Register file design considerations in dynamically scheduled processors

K.I. Farkas, N.P. Jouppi, P. Chow
Proceedings. Second International Symposium on High-Performance Computer Architecture  
We do work in the design, fabrication and packaging of hardware; language processing and scaling issues in system software design; and the exploration of new applications areas that are opening up with  ...  System design is the art of composing systems which use each level of technology in an appropriate balance.  ...  Acknowledgments The research described in this paper has been partially funded by the Natural Sciences and Engineering Research Council of Canada and by Digital Equipment Corporation.  ... 
doi:10.1109/hpca.1996.501172 dblp:conf/hpca/FarkasJC96 fatcat:ih3hsp2szbf4fitqu3fpyfipv4

Configurable Fault-Tolerance for a Configurable VLIW Processor [chapter]

Fakhar Anjam, Stephan Wong
2013 Lecture Notes in Computer Science  
Parity checking is utilized to detect errors in the instruction and data memories and the general register file (GR), while triple modular redundancy (TMR) approach is employed for all the synchronous  ...  The permanently enabled and the run-time configurable designs consume almost similar dynamic power.  ...  Parity checking is utilized to detect errors in the instruction and data memories, and the general register files (FPGA implementation).  ... 
doi:10.1007/978-3-642-36812-7_16 fatcat:aagbzgduyndk7brigcdaix6kxa

Architectural and compiler strategies for dynamic power management in the COPPER project

Azevedo, Cornea, Issenin, Gupta, Dutt, Nicolau, Veidenbaum
2001 Innovative Architecture for Future Generation High-Performance Processors and Systems IWIA-01  
In particular, we discuss our techniques for compiler controlled dynamic register file reconfiguration and profile-driven dynamic clock frequency and voltage scaling.  ...  We evaluate the effectiveness of power scheduling heuristics based on these techniques in complying with desired power and performance constraints for a given application.  ...  In this paper we focus on dynamic register file reconfiguration, frequency and voltage scaling.  ... 
doi:10.1109/iwia.2001.955194 fatcat:l6oyaaycqfbzzg76icbo6sdeti

An Energy Efficient Register File Architecture for VLIW Streaming Processors on FPGAs

2019 International Journal of Engineering and Advanced Technology  
The design of a register file with large scalability, high bandwidth, and energy efficiency is the major issue in the execution of streaming Very Long Instruction Word (VLIW) processors on Field Programmable  ...  This new IDRF is compared with the existing Central Register File (CRF) and the Distributed Register File (DRF) architectures on parameters such as kernel performance, circuit area, access delay, dynamic  ...  PRIOR WORK The traditional use of Centralized Register File (CRF) is to implement multi-ported register files in processors.  ... 
doi:10.35940/ijeat.a1003.1291s319 fatcat:bbewoggfxbbzhk6apxppy6cuf4

Predictable CPU Architecture Designed for Small Real-Time Application - Concept and Theory of Operation

Nicoleta Cristina, Ionel ZAGAN, Vasile Gheorghita
2015 International Journal of Advanced Computer Science and Applications  
An original implementation of a MIPS processor with thread interleaved pipeline is obtained, using dynamic scheduling of hard real-time tasks and interrupts.  ...  The new proposed architecture uses replication and remapping techniques for the program counter, the register file, and the pipeline registers and is implemented with a FPGA device.  ...  Thus, each task scheduled by the nHSE has a distinct program counter (PC), a separated bank in the Register file, and a distinct set of pipeline registers (IF/ID -Instruction Fetch-Instruction Decode stage  ... 
doi:10.14569/ijacsa.2015.060406 fatcat:bmelqltxg5hpvj4u6wwp2tnj5e

A Technology-Scalable Architecture for Fast Clocks and High ILP [chapter]

Karthikeyan Sankaralingam, Ramadass Nagarajan, Doug Burger, Stephen W. Keckler
2001 Interaction between Compilers and Computer Architectures  
CMOS technology scaling poses challenges in designing dynamically scheduled cores that can sustain both high instruction-level parallelism and aggressive clock frequencies.  ...  In this paper, we present a new architecture that maps compiler-scheduled blocks onto a two-dimensional grid of ALUs.  ...  Rau proposed a split-issue mechanism to separate register read and execute from writeback and a delay buffer to support dynamic scheduling for VLIW processors [14] .  ... 
doi:10.1007/978-1-4757-3337-2_7 fatcat:yibv6xtijjdhfcdlqve62kqnmy

MICROTHREADING A MODEL FOR DISTRIBUTED INSTRUCTION-LEVEL CONCURRENCY

CHRIS JESSHOPE
2006 Parallel Processing Letters  
The model is fine grain and provides synchronisation in a distributed register file, making it a promising candidate for scalable chip-multiprocessors.  ...  The model supports deterministic distribution of code fragments and dynamic scheduling of instructions from within those fragments.  ...  Such dynamic resolution is only possible because of the dynamic distribution and scheduling in this model.  ... 
doi:10.1142/s0129626406002587 fatcat:4khonednobh65av53v7q7d64j4

An Approach of nMPRA Architecture using Hardware Implemented Support for Event Prioritization and Treating

Ionel ZAGAN, Nicoleta Cristina, Vasile Gheorghita
2017 International Journal of Advanced Computer Science and Applications  
The present paper presents the hardware support of the nMPRA processor (Multi Pipeline Register Architecture) dedicated to treating time events, interrupt events and events associated with synchronization  ...  Because in real time systems the treatment of events is a very important aspect, this paper describes both the mechanism implemented in hardware for prioritizing and treating multiple events, and the experimental  ...  ACKNOWLEDGMENT This work was partially supported from the project "Integrated Center for research, development and innovation in Advanced Materials, Nanotechnologies, and Distributed Systems for fabrication  ... 
doi:10.14569/ijacsa.2017.080206 fatcat:j5oudukrjzhhtpuzsnf7q4sj6a

Asymmetrically Banked Value-Aware Register Files

Shuai Wang, Hongyan Yang, Jie Hu, Sotirios G. Ziavras
2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)  
register file designs.  ...  Designing high-performance low-power register files is of critical importance to the continuation of current performance advances in wide-issue and deeply-pipelined superscalar microprocessors.  ...  Introduction High-performance dynamically-scheduled processors rely on register renaming to eliminate false data dependences among the dynamic instruction stream and to expose instruction level parallelism  ... 
doi:10.1109/isvlsi.2007.27 dblp:conf/isvlsi/WangYHZ07 fatcat:ci3tppztv5febp6onhwskq2odu

Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA

Robert Dimond, Oskar Mencer, Wayne Luk
2006 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines  
We generate over 150 optimized processor designs for two FPGA platforms, two processor architectures and six different benchmarks at four different clock rates and achieve consistent measured dynamic power  ...  Our results are applicable beyond processor optimization, quantifying the benefits of practical switching reduction and highlighting non-obvious pitfalls and complexities in dynamic power optimization.  ...  [9] quantify the effect of pipelining on energy per-operation in FPGAs and demonstrate considerable dynamic power reduction.  ... 
doi:10.1109/fccm.2006.31 dblp:conf/fccm/DimondML06 fatcat:xtmmktjntrfuhe7jyxy27lon6u

Instruction Level Parallelism through Microthreading—A Scalable Approach to Chip Multiprocessors

Kostas Bousias, Nabil Hasasneh, Chris Jesshope
2005 Computer journal  
It supports distributed instruction issue and a fully scalable register file, which implements a distributed, shared-register model of communication and synchronization between multiple processors on a  ...  Wide-issue width also requires a large multi-ported register file, so that each instruction can read and write its operands simultaneously.  ...  requires considerable ILP.  ... 
doi:10.1093/comjnl/bxh157 fatcat:d73gokblevbtjcp6rwsz3y5s3q

Scaling to the end of silicon with EDGE architectures

D. Burger, S.W. Keckler, K.S. McKinley, M. Dahlin, L.K. John, C. Lin, C.R. Moore, J. Burrill, R.G. McDonald, W. Yoder
2004 Computer  
In our scheduling taxonomy, a superscalar processor is a dynamic placement, dynamic issue (DPDI) machine. 4 bear considerable resemblances to intrablock execution in EDGE architectures.  ...  In contrast, EDGE processors issue the set of instructions dynamically in mapped blocks, which makes them considerably more general purpose. power ceiling; thus, they must support power-efficient performance  ... 
doi:10.1109/mc.2004.65 fatcat:kvdia4bm2velfnlle57bt6qcpy

A Run-Time Task Migration Scheme for an Adjustable Issue-Slots Multi-core Processor [chapter]

Fakhar Anjam, Quan Kong, Roel Seedorf, Stephan Wong
2012 Lecture Notes in Computer Science  
The design is implemented in a Xilinx Virtex-6 FPGA.  ...  In this paper, we present a run-time task migration scheme for an adjustable/reconfigurable issue-slots very long instruction word (VLIW) multi-core processor.  ...  The opinions expressed in this paper are of the authors only and in no way reflect the European Commissions opinions.  ... 
doi:10.1007/978-3-642-28365-9_9 fatcat:fig2crumcrdqvg7iuxwtyxpkye

FlexGrip: A soft GPGPU for FPGAs

Kevin Andryc, Murtaza Merchant, Russell Tessier
2013 2013 International Conference on Field-Programmable Technology (FPT)  
Over the past decade, soft microprocessors and vector processors have been extensively used in FPGAs for a wide variety of applications.  ...  In this paper, we describe the implementation of FlexGrip, a soft GPGPU architecture which has been optimized for FPGA implementation.  ...  The Write stage stores intermediate data in the vector register file, memory addresses in the address register file, and predicate flags in the predicate register file.  ... 
doi:10.1109/fpt.2013.6718358 dblp:conf/fpt/AndrycMT13 fatcat:7ey67anaezbj7p7dgz2qtlnzty

Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA

Nguyen My Qui, Chang Hong Lin, Poki Chen
2020 IEEE Access  
An instruction scheduler is integrated to dynamically schedule independent instructions into the VLIW instruction format.  ...  INDEX TERMS very long instruction word (VLIW), RISC-V, microprocessor, dynamic scheduling, fieldprogrammable gate arrays (FPGA)  ...  Dynamic instruction scheduling VLIW (DISVLIW) [17] , which is a hybrid architecture with inherited features, such as ILP exploitation at the compile time of the VLIW processor and dynamic scheduling at  ... 
doi:10.1109/access.2020.3024851 fatcat:dmuncwyibva4hivtx3n45bsbyq
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