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Implementation of Low Cost Memory Subsystem for Low-end IoT Devices
2019
International Journal of Reliable Information and Assurance
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The proposed method solves the data placement problem for multi-bank memory and maximizes system performance by actively using multi-bank memory. ...
In other words, a compiler must be provided to generate program code for parallel memory access. This is because traditional compilers generate program code for sequential access. ...
After the scheduling and register allocation steps, their paper [1] states that the placement of local data variables to dual memory banks. It uses meta-assembly code what they defined. ...
doi:10.21742/ijria.2019.7.2.04
fatcat:wdo35fwdzjg6baxnziqd3vtsyu
Register promotion by sparse partial redundancy elimination of loads and stores
1998
SIGPLAN notices
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We present two different algorithms for performing speculative code motion: the conservative speculation algorithm used in the absence of profile data, and the the profile-driven speculation algorithm ...
We discuss how to effect speculative code motion in the SSAPRE framework. ...
Pseudo-registers have no alias, and the process of assigning them to real registers involves only renaming them. Thus, using pseudo-registers simplifies the register allocator's job. ...
doi:10.1145/277652.277659
fatcat:fbbiwr7acvdi5ljkw7j7py42tm
Register promotion by sparse partial redundancy elimination of loads and stores
1998
Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation - PLDI '98
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We present two different algorithms for performing speculative code motion: the conservative speculation algorithm used in the absence of profile data, and the the profile-driven speculation algorithm ...
We discuss how to effect speculative code motion in the SSAPRE framework. ...
Pseudo-registers have no alias, and the process of assigning them to real registers involves only renaming them. Thus, using pseudo-registers simplifies the register allocator's job. ...
doi:10.1145/277650.277659
dblp:conf/pldi/ChowKLLT98
fatcat:mf3u5o7mnvajlhf4bf5jarqxri
Decoding-Aware Compression of FPGA Bitstreams
2011
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Our proposed technique outperforms the existing compression approaches by 15%, while our decompression hardware for variable-length coding is capable of operating at the speed closest to the best known ...
field-programmable gate array-based decoder for fixed-length coding. ...
We determine the code type by checking CR and BR, then assemble the code using bits buffered in different shift registers. ...
doi:10.1109/tvlsi.2009.2035704
fatcat:xuvtvp7d5jaajhrn2r6emmigta
A New Compiler for Space-Time Scheduling of ILP Processors
2011
International Journal of Computer and Electrical Engineering
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The code generation for parallel register share architecture involves some issues that are not present in sequential code compilation and is inherently complex. ...
To resolve such issues, a consistency contract between the code and the machine can be defined and a compiler is required to preserve the contract during the transformation of code. ...
CONTROL LOCALIZATION Control localization is the technique of treating a branchcontaining code sequence as a single unit during assignment and scheduling. ...
doi:10.7763/ijcee.2011.v3.375
fatcat:zkukpxggjvbv5nhacioojp6uma
Register allocation using lazy saves, eager restores, and greedy shuffling
1995
Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation - PLDI '95
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Perhaps the most well-known of these is to decide which variables to assign to registers so that there is no conflict [5] . ...
Furthermore, it is successful even in the presence of anonymous procedure calls, which typically cause interprocedural register allocation techniques to break down. ...
His technique, however, is applied after variables have been assigned to callee-save registers. ...
doi:10.1145/207110.207125
dblp:conf/pldi/BurgerWD95
fatcat:yeq2kcvzg5cnvj4mpaykxebhzm
Register allocation using lazy saves, eager restores, and greedy shuffling
1995
SIGPLAN notices
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Perhaps the most well-known of these is to decide which variables to assign to registers so that there is no conflict [5] . ...
Furthermore, it is successful even in the presence of anonymous procedure calls, which typically cause interprocedural register allocation techniques to break down. ...
His technique, however, is applied after variables have been assigned to callee-save registers. ...
doi:10.1145/223428.207125
fatcat:j3f6aqniprgvzcd2z2ciw4wn34
B2P2
2010
Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems - SCOPES '10
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Though the Use-Last technique is effective in reducing i-TLB power, there is scope to further improve its effectiveness by changing the relative code placement of the program. ...
In this work, we formulate the code placement problem to minimize the page-switches in a program. ...
Related Code Placement Techniques Over the years, researchers have developed various code placement techniques targeting power and performance issues in embedded processors. Xianglong et al. ...
doi:10.1145/1811212.1811215
dblp:conf/scopes/JeyapaulS10
fatcat:fw7wajl4g5ghddeluezxrvazly
Efficient spill code for SDRAM
2003
Proceedings of the international conference on Compilers, architectures and synthesis for embedded systems - CASES '03
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This is particularly useful in connection with register allocation where spill code may need to save and restore multiple registers. ...
In this paper we investigate the use of SDRAM for optimization of spill code. ...
We thank Douglas Comer for his suggestions and for providing us with access to IXP-1200 network processors. We were supported by Intel and by a National Science Foundation ITR Award number 0112628. ...
doi:10.1145/951710.951716
dblp:conf/cases/NandivadaP03
fatcat:gvndjnlbgvdqno7rdf4gkf6s5q
Efficient spill code for SDRAM
2003
Proceedings of the international conference on Compilers, architectures and synthesis for embedded systems - CASES '03
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This is particularly useful in connection with register allocation where spill code may need to save and restore multiple registers. ...
In this paper we investigate the use of SDRAM for optimization of spill code. ...
We thank Douglas Comer for his suggestions and for providing us with access to IXP-1200 network processors. We were supported by Intel and by a National Science Foundation ITR Award number 0112628. ...
doi:10.1145/951713.951716
fatcat:h5u6jprcnjgr3fuke3ytfhxv54
Return value placement and tail call optimization in high level languages
1999
The Journal of Logic Programming
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This can be seen as realizing a restricted Ibrm of inter-procedural register allocation, and avoids the disadvantages associated with the fixed register and lixed men lory OUtl~Ut placement policies. ...
Implementations of such languages typically rely on fixed placement policies: most functional language implementations return output values in registers, while most logic programming systems return outputs ...
The first author was also supported by graduate fellowships from the US Office of Naval Research and AT&T Bell Laboratories. ...
doi:10.1016/s0743-1066(98)80001-0
fatcat:7wnox4rdezbp5azup7s57xt6n4
Improvement Energy Efficiency for a Hybrid Multibank Memory in Energy Critical Applications
2020
Tehnički Vjesnik
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The proposed technique solves this negative effect of non-volatile memory by using efficient data placement technique and hybrid memory architecture. ...
Based on the problem definition, we proposed two efficient algorithms to determine the placement of data to the multibank memory. ...
register allocation technique. ...
doi:10.17559/tv-20200826040830
fatcat:hesbtyl5m5hwno3xnci6u6urty
Building a retargetable local instruction scheduler
1998
Software, Practice & Experience
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Using the techniques described here, an efficient local instruction scheduler that generates excellent code for instruction-level parallel architectures can be built. ...
This paper explores using one scheduler for a number of different architectures and the ramifications of this. ...
DRAFT is that many register assignment algorithms attempt to use the minimal number of registers. ...
doi:10.1002/(sici)1097-024x(199803)28:3<249::aid-spe152>3.0.co;2-x
fatcat:weipmmc6r5ckfoknjpf5syxv7a
System-level Scheduling on Instruction Cell Based Reconfigurable Systems
2006
Proceedings of the Design Automation & Test in Europe Conference
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Unlike other typical scheduling methods, it considers the placement and routing effect, register assignment and advanced operation chaining compilation technique to generate higher performance scheduled ...
code. ...
The CRS algorithm is based on the list scheduling algorithm and adopts the advanced operation chaining technique and considers the effects of register assignment, power consumption, placement and routing ...
doi:10.1109/date.2006.243762
dblp:conf/date/YiNMKAL06
fatcat:dwh5mbmy3jdo5krzxw5z6evvwq
Progressive spill code placement
2009
Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems - CASES '09
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Several authors propose a separation of the problem into decoupled sub-tasks including spilling, allocation, assignment, and coalescing. ...
Register allocation has gained renewed attention in the recent past. ...
The objective is to assign hardware registers to program variables. Program variables that are not alive at the same time can use the same register. ...
doi:10.1145/1629395.1629408
dblp:conf/cases/EbnerSK09
fatcat:apq3vd6cnbcc5dqif7nbay4lwe
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