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Critical-Trunk-Based Obstacle-Avoiding Rectilinear Steiner Tree Routings and Buffer Insertion for Delay and Slack Optimization
2011
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Obstacle-avoiding rectilinear Steiner tree (OARST) construction is an essential routing problem. ...
The proposed multisource single-target maze routing is first employed to identify the critical trunks, and the critical-trunk-based tree growth mechanism connects the unconnected pins to critical trunks ...
[5] proposed a bounded radius-ratio Steiner minimum tree based on a rectilinear minimum spanning tree (RMST) and the radius-ratio for each sink. ...
doi:10.1109/tcad.2011.2150222
fatcat:3zoyiwapxjenpogj5dpe37wvsu
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
2005
Proceedings of the 2005 international symposium on physical design - ISPD '05
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In this paper, we present a very fast and accurate rectilinear Steiner minimal tree (RSMT) 1 algorithm called FLUTE. ...
efficient implementation of Prim's rectilinear minimum spanning tree (RMST) algorithm. ...
Cheng for providing the source code of RST-T and Prof. Hai Zhou for providing the source code of SPAN. ...
doi:10.1145/1055137.1055145
dblp:conf/ispd/ChuW05
fatcat:gng3lvps2ndddflydsrm2c6odq
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
2008
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we present a very fast and accurate rectilinear Steiner minimal tree (RSMT) algorithm called FLUTE. ...
efficient implementation of Prim's rectilinear minimum spanning tree (RMST) algorithm. ...
[13] proposed an algorithm called Refined Single Trunk Tree (RST-T) to reduce the length of STST by a refining procedure. ...
doi:10.1109/tcad.2007.907068
fatcat:p5lcm5tzgjeflmmgbgt222dtm4
Performance optimization of VLSI interconnect layout
1996
Integration
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This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization ...
and embedding, planar clock routing, buffer and wire sizing for clock nets, non-tree clock routing, and clock schedule optimization. ...
In [62] , Lim et al. proposed perjbrmance-oriented rectilinear Steiner trees for the interconnect optimization problem. ...
doi:10.1016/s0167-9260(96)00008-9
fatcat:jt7444lufzaf5hxi7vg22qvvue
IPR: An Integrated Placement and Routing Algorithm
2007
Proceedings - Design Automation Conference
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As a first attempt to this novel approach, we focus on routability issue. We call the proposed algorithm for routing congestion minimization IPR (Integrated Placement and Routing). ...
As a result, placement solution considered to be good by primitive interconnect models may turn out to be poor after routing. ...
In [4] , Jariwala and Lillis employed a single-trunk Steiner tree model to reduce congestion in FPGAs. Recently, Roy et al. ...
doi:10.1109/dac.2007.375125
fatcat:obtzew73mjasbp6tbjcrc6gi5y
IPR
2007
Proceedings - Design Automation Conference
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As a first attempt to this novel approach, we focus on routability issue. We call the proposed algorithm for routing congestion minimization IPR (Integrated Placement and Routing). ...
As a result, placement solution considered to be good by primitive interconnect models may turn out to be poor after routing. ...
In [4] , Jariwala and Lillis employed a single-trunk Steiner tree model to reduce congestion in FPGAs. Recently, Roy et al. ...
doi:10.1145/1278480.1278496
dblp:conf/dac/PanC07
fatcat:n6vavhuzsfcoherurf4jtubeqy
Global and detailed routing
[chapter]
2009
Electronic Design Automation
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Zhe-Wei Jiang of National Taiwan University for his help with Section 12.6. 3 .1. ...
We also thank the authors of ] for their help with the formulation of the programming assignment in Exercise 12.11, and Mr. ...
rectilinear Steiner tree (MRST) be p and q, respectively. ...
doi:10.1016/b978-0-12-374364-0.50019-9
fatcat:ybywesjpgjgppotezavllr3vmi
Synthesis of clock and power/ground networks
[chapter]
2009
Electronic Design Automation
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A power/ground (P/G) supply network provides a reference voltage for determining the status of a transistor (on or off) and also the current for switching a transistor. ...
The chapter then examines the automated analysis, synthesis, and optimization of such large-scale interconnection networks in two sections, one for clock networks and the other one for power supply networks ...
Chung-Wen Albert Tsao of Cadence Design Systems for reviewing the chapter. ...
doi:10.1016/b978-0-12-374364-0.50020-5
fatcat:ghkcsxz6hvfapfwsvke66z7gme
The circuit and physical design of the POWER4 microprocessor
2002
IBM Journal of Research and Development
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The complexity and size of POWER4, together with its high operating frequency, presented a number of significant challenges for its multisite design team. ...
For each of the four hierarchies, the logic design and simulation were able to progress in parallel with the circuit design of that entity, with a final formal verification step to ensure equivalence [ ...
These final sector trees all drive a single full-chip clock grid (appearing at the top of Figure 7 ) at 1024 evenly spaced points. ...
doi:10.1147/rd.461.0027
fatcat:wp4ojp7zyfam5nhtajbfdfh2uy
Accurate prediction of physical design characteristics for random logic
Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors
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In this paper, we present an accurate model for prediction of physical desi n characteristics, such as interconnection lengths a n f layout areas, for standard cell layouts. ...
Accurate prediction of physical design characteristics are useful for floorplanning, for evaluating the fit of a logic design to a fabrication technology, and for studying placement algorithms. ...
A single trunk is used to connect pins of any net inside the channel. ...
doi:10.1109/iccd.1989.63337
fatcat:x6hjxk3wkrdmzdouqm2sedayaa
FLUTE: fast lookup table based wirelength estimation technique
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.
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In this paper, we present a novel wirelength estimation technique called FLUTE. ...
Our technique is based on pre-computed lookup table to make wirelength estimation very fast and very accurate for low degree 1 nets. ...
The table stores the set of POWVs associated with each vertical sequence for low degree nets. We proposed an algorithm based on boundary compaction to generate the sets of POWVs. ...
doi:10.1109/iccad.2004.1382665
dblp:conf/iccad/Chu04
fatcat:juiybhvw7zhmnoa7v4dhtwumne
Layer assignment and routing optimization for advanced technologies
[article]
2018
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Through the combination of pins and inserted points with a set of rectilinear connections (RCs), we are able to achieve a rectilinear Steiner tree. ...
For the non-routed groups, we estimate the wirelength based on Rectilinear Steiner Minimum Tree (RSMT) algorithm. Thus the reported wire-length represents the routing condition of a whole design. ...
groups. • A refinement stage allows appropriate twisting routes to reduce the source-to-sink distance deviation. ...
doi:10.15781/t2db7w87m
fatcat:wneg2fhgg5cxhh7hacd2up536e
Dagstuhl Seminar on On-line Algorithms Summary The Dagstuhl meeting on On-line Algorithms brought together 55 researchers with affiliations in Argentina List of Participants On-line Algorithms Abstracts A Survey of Self-Organizing Data-Structures
Czechia
unpublished
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presented by • Daniel Sleator (On the history of on-line algorithms) • Avrim Blum (On-line algorithms in machine learning) • Sandy Irani (Paging problems) • Christos Papadimitriou (Non-standard models for ...
We had a wine-and-cheese party every evening; on Tuesday evening the party included an open problem session organized by David Johnson. ...
tree problem, the minimum Steiner tree problem, the weighted and unweighted matching problems, and the traveling salesman problem. ...
fatcat:46smtqkanfd3jlwrtfynsbhsdy
Quantum Mind 2003, Consciousness, Quantum Physics and the Brain. March 15-19, 2003, The University of Arizona, Tucson, Arizona
2007
NeuroQuantology
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A relation between consciousness and quantum effects has been pondered for nearly a century, and in the past decades quantum processes in the brain have been invoked as explanations for consciousness and ...
Critics deride this comparison as a mere "minimization of mysteries" and quickly point out that the brain is too warm for quantum computation which in the technological realm requires extreme cold to avoid ...
This asymmetry was predicted to result in a difference in the ERP wave forms generated under the two conditions. ...
doi:10.14704/nq.2003.1.3.23
fatcat:e76cv2ivqjdbxolv2hbls67gqu
Botanical Aspects of the Environment and Economy at Tell Tayinat from the Bronze to Iron Ages (ca. 2.200 – 600 BCE), in south-central Turkey
[article]
2020
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The general aim of the present dissertation is to increase our understanding of the diachrony of agricultural production and of the growing conditions of crop plants of Tell Tayinat as well as the wider ...
The Eastern Mediterranean Basin including Northern Levant has a long history of archaeological research. ...
Some investigations are based on one particular storage context, often only including a single sample dominated by a single crop plant. ...
doi:10.15496/publikation-39877
fatcat:izh4mpk6sfhevnb7unm2klic3e
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