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Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder [article]

P. Balasubramanian, D.L. Maskell, N.E. Mastorakis
2019 arXiv   pre-print
in CT and PCTP respectively compared to an optimum QDI early output RCA, ii) 16.5% and 15.8% reductions in CT and PCTP respectively compared to an optimum relative-timed RCA, iii) 32.9% and 35.9% reductions  ...  The cycle time (CT), which is the sum of forward and reverse latencies, governs the speed; and the product of average power dissipation and cycle time viz. the power-cycle time product (PCTP) defines the  ...  Edwards and W.B. Toms, “Redundant logic insertion and latency reduction in self-timed adders,” VLSI Design, vol. 2012, Article ID 575389, pp. 1-13, May 2012. 36. N.P.  ... 
arXiv:1903.09433v1 fatcat:5vswc63rb5hzrmqlea23hxxubu

Introducing redundant computations in a behavior for reducing BIST resources

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
1998 Proceedings of the 35th annual conference on Design automation conference - DAC '98  
A technique is presented for introducing redundant computations that reduce the BIST resource requirements of a data path without compromising the latency and functional resource constraints.  ...  The degree of freedom that can be exploited during scheduling and assignment to minimize BIST resources is often limited by the data dependencies of a behavior.  ...  McCluskey and Dr. LaNae J. Avra of the Center for Reliable Computing at Stanford University for providing the TOPS synthesis system.  ... 
doi:10.1145/277044.277191 dblp:conf/dac/ParulkarGB98 fatcat:zvu7hcs7tfho3cfve3kxeiohde

Carry checking/parity prediction adders and ALUs

M. Nicolaidis
2003 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In this paper, we present efficient self-checking implementations valid for all existing adder and arithmatic and logic unit (ALU) schemes (e.g., ripple carry, carry lookahead, skip carry schemes).  ...  Index Terms-Carry-lookahead adders and ALUs, parity prediction adders and ALUs, self-checking adders and ALUs, selfchecking circuits.  ...  Since adders and ALUs proposed in the literature are well-optimized circuits, no redundancies exist in these designs and the self-testing property holds true for all stuck-at faults.  ... 
doi:10.1109/tvlsi.2002.800526 fatcat:wo5szzoqjbad5ht2xak2dxahaq

Redundancy and testability in digital filter datapaths

L. Goodby, A. Orailoglu
1999 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Classes of redundant faults that arise in digital filter datapaths are described, and we propose a suite of techniques for identifying and eliminating the most common redundancies based on arithmetic optimization  ...  The approach is suitable as a front-end to more accurate fault simulation, or can be used in the design process to eliminate redundant logic.  ...  An example is adding and times a 6-bit input signal, producing a 13-bit result. Here, , , and , so a restricted-overflow redundancy will occur in this adder logic.  ... 
doi:10.1109/43.759079 fatcat:3dcf7h4szndtbd6k2cg67obdey

LH-CORDIC: Low Power FPGA Based Implementation of CORDIC Architecture

Sharath Inguva, Joseph Seventiline
2019 International Journal of Intelligent Engineering and Systems  
These three techniques are used to redesign the entire CORDIC logic stages thereby contributing in power consumption reduction.  ...  Then, we propose an adder based on the advanced Boolean logic technique.  ...  In seven rotation modules the designs are divided and in each rotation module there has two ordinary or self checking Subtractor modules /Adder modules.  ... 
doi:10.22266/ijies2019.0430.30 fatcat:jbwzzontsngqpgr5fofokurns4

Fast Radix-10 Multiplication Using Redundant BCD Codes

Alvaro Vazquez, Elisardo Antelo, Javier D. Bruguera
2014 IEEE transactions on computers  
In addition, new techniques are developed to reduce significantly the latency and area of previous representative highperformance implementations.  ...  Also, the available redundancy allows a fast and simple generation of multiplicand multiples in a carryfree way.  ...  ACKNOWLEDGMENTS Work supported in part by Ministry of Science and Innovation of Spain, co-funded by the European Regional Development Fund (ERDF/FEDER), under contract TIN2010-17541, and by the Xunta de  ... 
doi:10.1109/tc.2014.2315626 fatcat:wdlm4xjgjra77jngt4ktdjmxeu

Introducing redundant computations in RTL data paths for reducing BIST resources

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
2001 ACM Transactions on Design Automation of Electronic Systems  
Introduction of redundant computations is performed without compromising the latency and functional resource requirement of the behavior.  ...  A technique for identifying potential BIST resource sharing problems in a behavior and resolving them by redundant computation is presented.  ...  McCluskey and Dr. LaNae J. Avra of the Center for Reliable Computing at Stanford University for providing the TOPS synthesis system.  ... 
doi:10.1145/383251.383253 fatcat:pnw6af75yfhefpkhdiyd2jfzke

Robust low power computing in the nanoscale era

Todd Austin
2006 Proceedings of the 19th annual symposium on Integrated circuits and systems design - SBCCI '06  
in fault strengthen interest in fault--tolerance tolerance • • renew interest in self renew interest in self--healing healing How are they related?  ...  (40%) corruption (40%) Faults in combinational logic can cause double Faults in combinational logic can cause double and multiple bit errors and multiple bit errors Multiple Bit-flip Distribution  ... 
doi:10.1145/1150343.1150352 dblp:conf/sbcci/Austin06 fatcat:7cdhgdke4raevpc7m2plec6fjq

Complexity-Aware Quantization and Lightweight VLSI Implementation of FIR Filters

Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu
2011 EURASIP Journal on Advances in Signal Processing  
In our experiments, the proposed framework saves 49% ∼ 51% additions of the filters with 2's complement coefficients and 10% ∼ 20% of those with conventional signed-digit representations for comparable  ...  Moreover, the bit-serialization can reduce 33% ∼ 35% silicon area for less timing-critical applications.  ...  The authors would like to thank David Novo and the anonymous reviewers for their helps on improving this paper.  ... 
doi:10.1155/2011/357906 fatcat:je3rhzevxjal7mg4alhxyyjiaq

Fault Secure Datapath Synthesis Using Hybrid Time and Hardware Redundancy

K. Wu, R. Karri
2004 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper presents a register transfer level concurrent error detection (CED) technique that uses hybrid time and hardware redundancy to optimize the time and area overhead associated with fault security  ...  Index Terms-Asynchronous datapath, differential cascode voltage switch logic (DCVSL), dynamic circuits, self-checking (SC).  ...  Since the normal design uses just one adder/subtractor, we have added one more adder/subtractor in the time redundancy-based fault-secure design.  ... 
doi:10.1109/tcad.2004.835132 fatcat:bgymbnb2gfbthcrqj4kkryrbfm

Designing asynchronous circuits for low power: an IFIR filter bank for a digital hearing aid

L.S. Nielsen, J. Sparso
1999 Proceedings of the IEEE  
This has been achieved by the use of asynchronous control and data-path logic, an improved RAM design, and by a mechanism that adapts the number range to the actual need (exploiting the fact that typical  ...  The principles and techniques explained in this paper are of a general nature, and they apply to the design of asynchronous lowpower digital signal-processing circuits in a broader perspective.  ...  Christensen from Oticon, Inc. for many good discussions, and for sharing design details of the hearing aid design. The CAD tools used in the project were provided through EUROPRACTICE.  ... 
doi:10.1109/5.740020 fatcat:jbquwdlifraihhckxvn4igcxvy

Asynchronous circuit design

2002 ChoiceReviews  
This has been achieved by the use of asynchronous control and data-path logic, an improved RAM design, and by a mechanism that adapts the number range to the actual need (exploiting the fact that typical  ...  The principles and techniques explained in this paper are of a general nature, and they apply to the design of asynchronous lowpower digital signal-processing circuits in a broader perspective.  ...  Christensen from Oticon, Inc. for many good discussions, and for sharing design details of the hearing aid design. The CAD tools used in the project were provided through EUROPRACTICE.  ... 
doi:10.5860/choice.39-2818 fatcat:6uhfw7oi7jcnvlhf3tjfzq4abq

Computer aided design of fault-tolerant application specific programmable processors

M. Potkonjak, K. Kim, R. Karri
2000 IEEE transactions on computers  
In this paper, we do not consider concurrent error detection.  ...  In this paper, we present two low-cost approaches to graceful degradation-based permanent fault tolerance of ASPPs.  ...  An algorithm that intertwines checkpoint insertion and scheduling (of operations in the input algorithm to clock cycles) to synthesize self-recovering microarchitectures for supporting fault-recovery in  ... 
doi:10.1109/12.895942 fatcat:2aaeuskl4zbw3emjcaehhmihty

The design and verification of a high-performance low-control-overhead asynchronous differential equation solver

K.Y. Yun, P.A. Beerel, V. Vakilotojar, A.E. Dooply, J. Arceo
1998 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In addition, symbolic model checking techniques are described that were used to gain higher confidence in the correctness of the timed distributed control.  ...  The techniques to reduce completion sensing overhead and hide control overhead at the circuit, architectural, and protocol levels are discussed.  ...  Acknowledgment Authors would like to thank Jim Garside at University of Manchester for providing ARM benchmarks and many insightful discussions.  ... 
doi:10.1109/92.736138 fatcat:mi3nem5lojhnznlicbavwnopte

Implementation of ALU Using Asynchronous Design

P Amrutha
2012 IOSR Journal of Electronics and Communication Engineering  
Here ALUs are designed with delay insensitive dual rail four phase logic and CMOS domino logic. It ensures economy in silicon area and potentially for low power consumption.  ...  Also simulation results, show significant reduction in the number of transistors as well as delay.  ...  The Adder Circuit in ALU This ALU has no special fast carry logic and performs addition with a chain of thirty two full adders.  ... 
doi:10.9790/2834-0360712 fatcat:qnziz43njfhgblnina7p2mm4dm
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