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Reduction of interpolants for logic synthesis

John D. Backes, Marc D. Riedel
2010 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)  
Craig Interpolation is a state-of-the-art technique for logic synthesis and verification, based on Boolean Satisfiability (SAT).  ...  This, in turn, reduces the cost of the logic that is generated for functional dependencies.  ...  Boolean Satisfiability (SAT) has found wide applicability for problems in logic synthesis and verification [1] , [9] , [11] .  ... 
doi:10.1109/iccad.2010.5654209 dblp:conf/iccad/BackesR10 fatcat:qjseqqakzrhcdop2uhb76jeuha

Invariant-Strengthened Elimination of Dependent State Elements

Michael L. Case, Alan Mishchenko, Robert K. Brayton, Jason Baumgartner, Hari Mony
2008 2008 Formal Methods in Computer-Aided Design  
This work presents a technology-independent synthesis optimization that is effective in reducing the total number of state elements of a design.  ...  It works by identifying and eliminating dependent state elements which may be expressed as functions of other registers. For scalability, we rely exclusively on SATbased analysis in this process.  ...  ACKNOWLEDGEMENTS The authors would like to thank Per Bjesse for all his help in preparing this paper for publication.  ... 
doi:10.1109/fmcad.2008.ecp.6 dblp:conf/fmcad/CaseMBBM08 fatcat:3mn25srtfrem3iwz634zd3gt7e

Games and Decisions for Rigorous Systems Engineering (Dagstuhl Seminar 12461)

Nikolaj Bjorner, Krishnendu Chatterjee, Laura Kovacs, Rupak M. Majumdar, Marc Herbstritt
2013 Dagstuhl Reports  
This report documents the program and the outcomes of the Dagstuhl Seminar 12461 "Games and Decisions for Rigorous Systems Engineering".  ...  The seminar brought together researchers working in rigorous software engineering, with a special focus on the interaction between synthesis and automated deduction.  ...  We introduce a method for automated parameterized verification of fault-tolerant distributed algorithms.  ... 
doi:10.4230/dagrep.2.11.45 dblp:journals/dagstuhl-reports/BjornerCKM12 fatcat:gs36midqlvfhzky6v7ebawumtq

Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization

Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu, Chiu-Han Hsiao, Sy-Yen Kuo
2011 2011 12th International Symposium on Quality Electronic Design  
By synthesizing the bug conditions, we can derive input constraints for the software so that the hardware bugs will never be exposed.  ...  To facilitate the use of our methodology, we also propose a novel resynthesis technique to reduce the complexity of the constraints.  ...  Craig Interpolation Craig interpolation is a technique originated in mathematical logic [4] . Recently, it has become popular in verification and logic synthesis [2] , [11] , [12] .  ... 
doi:10.1109/isqed.2011.5770722 dblp:conf/isqed/ChangCCJLHK11 fatcat:zqlzpjjeizht3fbejlyoea6bjm

Speculative reduction-based scalable redundancy identification

H. Mony, J. Baumgartner, A. Mishchenko, R. Brayton
2009 2009 Design, Automation & Test in Europe Conference & Exhibition  
In this paper, we study the technique of speculative reduction for efficiently modeling redundancy assumptions.  ...  The process of sequential redundancy identification is the cornerstone of sequential synthesis and equivalence checking frameworks.  ...  This clearly illustrates the advantage of speculative reduction for interpolation.  ... 
doi:10.1109/date.2009.5090932 dblp:conf/date/MonyBMB09 fatcat:4buxh5neafdy5cidjlyohsmkou

Interpolating functions from large Boolean relations

Jie-Hong R. Jiang, Hsuan-Po Lin, Wei-Lun Hung
2009 Proceedings of the 2009 International Conference on Computer-Aided Design - ICCAD '09  
Boolean relations are an important tool in system synthesis and verification to characterize solutions to a set of Boolean constraints.  ...  From the scalability standpoint this paper demonstrates how interpolation can be exploited to extend determinization capacity.  ...  Acknowledgments The authors are grateful to Robert Brayton and Alan Mishchenko for valuable discussions. This work was supported in part by NSC grants 95-2218-E-002-064-MY3 and 96-2221-E-002-278-MY3.  ... 
doi:10.1145/1687399.1687544 dblp:conf/iccad/JiangLH09 fatcat:nktat45jgnc57o7sxoe7soa74q

Deduction Beyond First-Order Logic (Dagstuhl Seminar 17371)

Jasmin Christian Blanchette, Carsten Fuhs, Viorica Sofronie-Stokkermans, Cesare Tinelli, Marc Herbstritt
2018 Dagstuhl Reports  
Other practical problems need a mixture of first-order proof search and some more advanced reasoning (for instance, about higher-order formulas), or simply higher-level reasoning steps.  ...  This report documents the program and the outcomes of Dagstuhl Seminar 17371 "Deduction Beyond First-Order Logic."  ...  The proposed approach consists of over-approximations, underapproximations and their combination.  ... 
doi:10.4230/dagrep.7.9.26 dblp:journals/dagstuhl-reports/BlanchetteFST17 fatcat:yfc3wk2fwngc3i2dmjwrz3gsgi

ABC: An Academic Industrial-Strength Verification Tool [chapter]

Robert Brayton, Alan Mishchenko
2010 Lecture Notes in Computer Science  
ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs.  ...  A focus on the synergy of sequential synthesis and sequential verification leads to improvements in both domains.  ...  Acknowledgement This work has been supported in part by SRC contracts 1361.001 and 1444.001, NSF grant CCF-0702668, and the industrial sponsors: Abound Logic, Actel, Altera, Atrenta, Calypto, IBM, Intel  ... 
doi:10.1007/978-3-642-14295-6_5 fatcat:wobetxmdtbbvrlhvn5ihhmqjzu

Design Automation Framework for Application-Specific Logic-in-Memory Blocks

Qiuling Zhu, Kaushik Vaidyanathan, Ofer Shacham, Mark Horowitz, Larry Pileggi, Franz Franchetti
2012 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors  
This paper presents a design methodology for hardware synthesis of application-specific logic-in-memory (LiM) blocks.  ...  We evaluated a large design space of interpolation memories in sub-20 nm commercial CMOS technology by using the proposed design framework.  ...  ACKNOWLEDGEMENT The authors acknowledge the support of the C2S2 Focus Center, one of six research centers funded under the Focus Center Research Program (FCRP), a Semiconductor Research Corporation entity  ... 
doi:10.1109/asap.2012.21 dblp:conf/asap/ZhuVSHPF12 fatcat:ytjipw3w4vd33a5htlwjimg5ni

To SAT or Not to SAT: Scalable Exploration of Functional Dependency

J.-H.R. Jiang, Chih-Chun Lee, A. Mishchenko, Chung-Yang Huang
2010 IEEE transactions on computers  
logic synthesis and formal verification.  ...  Thereby, functional dependency can be detected effectively through incremental SAT solving, and the dependency function h, if it exists, is obtained through Craig interpolation.  ...  The authors are grateful to Robert Brayton for helpful discussions and to Ruei-Rung Lee for preparing some of the experimental data.  ... 
doi:10.1109/tc.2010.12 fatcat:idsqsxsccjdkjnscenwyjno3aa

Logic synthesis and circuit customization using extensive external don't-cares

Kai-Hui Chang, Valeria Bertacco, Igor L. Markov, Alan Mishchenko
2010 ACM Transactions on Design Automation of Electronic Systems  
Therefore we extend modern digital synthesis with a novel technique, called SWEDE, that makes use of extensive external don't-cares.  ...  For instance, third-party IP blocks used in a system-on-chip are often overdesigned for the requirements at hand.  ...  Craig Interpolation The concept of Craig interpolation originated in mathematical logic in 1957 and has recently become popular in formal verification.  ... 
doi:10.1145/1754405.1754411 fatcat:y42jli5llbeblkgn7eddcoqnvu

ROM-less LNS

R. Che Ismail, J. N. Coleman
2011 2011 IEEE 20th Symposium on Computer Arithmetic  
In particular, it is dominated by the need for large ROM tables for the storage of non-linear functions.  ...  logic.  ...  256 intervals per region, both of which can be readily synthesised in logic.  ... 
doi:10.1109/arith.2011.15 dblp:conf/arith/IsmailC10 fatcat:ob45ku4l2ng7zav2xapr5f7kbu

Scalable don't-care-based logic optimization and resynthesis

Alan Mishchenko, Robert Brayton, Jie-Hong Roland Jiang, Stephen Jang
2009 Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '09  
Experimental results on 6-input LUT networks after a high effort synthesis show substantial reductions in area and delay.  ...  When applied to 20 large academic benchmarks, the LUT counts and logic levels are reduced by 45.0% and 12.2%, respectively. The longest runtime for synthesis and mapping is about two minutes.  ...  ACKNOWLEDGMENTS We acknowledge the help of Zile Wei in running the place-and-route experiments in Table V of this article. We thank the anonymous reviewers for their helpful comments.  ... 
doi:10.1145/1508128.1508152 dblp:conf/fpga/MishchenkoBJJ09 fatcat:gwh2phiwsfef3juiclxlueaqpy

Scalable don't-care-based logic optimization and resynthesis

Alan Mishchenko, Robert Brayton, Jie-Hong R. Jiang, Stephen Jang
2011 ACM Transactions on Reconfigurable Technology and Systems  
Experimental results on 6-input LUT networks after a high effort synthesis show substantial reductions in area and delay.  ...  When applied to 20 large academic benchmarks, the LUT counts and logic levels are reduced by 45.0% and 12.2%, respectively. The longest runtime for synthesis and mapping is about two minutes.  ...  ACKNOWLEDGMENTS We acknowledge the help of Zile Wei in running the place-and-route experiments in Table V of this article. We thank the anonymous reviewers for their helpful comments.  ... 
doi:10.1145/2068716.2068720 fatcat:h3yagw5jvzc5haolfnzndsiu44

Suraq — A Controller Synthesis Tool Using Uninterpreted Functions [chapter]

Georg Hofferek, Ashutosh Gupta
2014 Lecture Notes in Computer Science  
We present Suraq, the first controller synthesis tool which uses uninterpreted functions for the abstraction.  ...  For example, the specification for the controller of a pipelined processor only has to state that the pipelined processor gives the same results as a non-pipelined reference design.  ...  Column 2 gives the time for the formula reductions, that is, the total time required for reading the specification, performing the formula reductions, and creating an input file for veriT.  ... 
doi:10.1007/978-3-319-13338-6_6 fatcat:gtdklh7zb5cuva3ex2i4i2wkrq
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