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Reducing translation lookaside buffer active power

Lawrence T. Clark, Byungwoo Choi, Michael Wilkerson
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
Here, power reduction techniques applicable to fully associative translation lookaside buffers, as well as other associative structures and dynamic register files, are described.  ...  Lowering active power dissipation is increasingly important for battery powered embedded microprocessors.  ...  Most of this dissipation is in the translation lookaside buffer (TLB) that provides physical address translation and page access permissions.  ... 
doi:10.1145/871510.871512 fatcat:ft4ioqhhz5gmlc7wvku7sn4kvu

Reducing translation lookaside buffer active power

Lawrence T. Clark, Byungwoo Choi, Michael Wilkerson
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
Here, power reduction techniques applicable to fully associative translation lookaside buffers, as well as other associative structures and dynamic register files, are described.  ...  Lowering active power dissipation is increasingly important for battery powered embedded microprocessors.  ...  Most of this dissipation is in the translation lookaside buffer (TLB) that provides physical address translation and page access permissions.  ... 
doi:10.1145/871506.871512 dblp:conf/islped/ClarkCW03 fatcat:kjxiwclrkrfxlpfoxgrjgx55su

Reducing translation lookaside buffer active power

L.T. Clark, Byungwoo Choi, M. Wilkerson
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.  
Here, power reduction techniques applicable to fully associative translation lookaside buffers, as well as other associative structures and dynamic register files, are described.  ...  Lowering active power dissipation is increasingly important for battery powered embedded microprocessors.  ...  Most of this dissipation is in the translation lookaside buffer (TLB) that provides physical address translation and page access permissions.  ... 
doi:10.1109/lpe.2003.1231825 fatcat:vle6ktdbnfeypmdedxxzvebwfm

Bit-Tactical: Exploiting Ineffectual Computations in Convolutional Neural Networks: Which, Why, and How [article]

Alberto Delmas, Patrick Judd, Dylan Malone Stuart, Zissis Poulos, Mostafa Mahmoud, Sayeh Sharify, Milos Nikolic, Andreas Moshovos
2018 arXiv   pre-print
TCL benefits both sparse and dense CNNs, natively supports both convolutional and fully-connected layers, and exploits properties of all activations to reduce storage, communication, and computation demands  ...  , and optionally the naturally occurring sparse effectual bit content of activations to improve performance and energy efficiency.  ...  Each tile has its own local slice of the AM, a local WM (not shown), an input activation buffer and an output activation buffer.  ... 
arXiv:1803.03688v1 fatcat:xdb3muwlufbb3aniet7ogy24uq

An Energy-Efficient Design Paradigm for a Memory Cell Based on Novel Nanoelectromechanical Switches [chapter]

Azam Seyedi, Vasileios Karakostas, Stefan Cosemans, Adrian Cristal, Mario Nemirovsky, Osman Unsal
2017 ICT - Energy Concepts for Energy Efficiency and Sustainability  
As a use case, we evaluate first-level instruction and data translation lookaside buffers (TLBs) with 16 nm CMOS technology at 2 GHz.  ...  The simulation results demonstrate that the NEMsCAM TLB reduces the energy consumption per search operation (by 27%), standby mode (by 53.9%), write operation (by 41.9%), and the area (by 40.5%) compared  ...  lookaside buffers (TLB).  ... 
doi:10.5772/66401 fatcat:mp5trf4vyrhzpfp35ky4pzabju

Arithmetic-Based Address Translation for Energy-Efficient Virtual Memory Support in Low-Power, Real-Time Embedded Systems

Xiangrong Zhou, Peter Petrov
2005 2005 18th Symposium on Integrated Circuits and Systems Design  
The experiments that we have performed on a set of embedded applications show power reductions in the range of80% to 95% compared to a general-purpose Translation Lookaside Buffer (TLB).  ...  Lookaside Buffer (TLB), are replaced with fast and energy efficient arithmetic add operations.  ...  The authors propose replacing the TLB with the more scalable and power efficient Synonym Lookaside Buffer, as it stores only the current synonym instances.  ... 
doi:10.1109/sbcci.2005.4286837 fatcat:v7lbguib3bbrlaffsspexjl32a

Arithmetic-based address translation for energy-efficient virtual memory support in low-power, real-time embedded systems

Xiangrong Zhou, Peter Petrov
2005 Proceedings of the 18th annual symposium on Integrated circuits and system design - SBCCI '05  
The experiments that we have performed on a set of embedded applications show power reductions in the range of80% to 95% compared to a general-purpose Translation Lookaside Buffer (TLB).  ...  Lookaside Buffer (TLB), are replaced with fast and energy efficient arithmetic add operations.  ...  The authors propose replacing the TLB with the more scalable and power efficient Synonym Lookaside Buffer, as it stores only the current synonym instances.  ... 
doi:10.1145/1081081.1081108 dblp:conf/sbcci/ZhouP05 fatcat:hjax7ty7dbhxpo5kznxbgtmu44

Entropy-based low power data TLB design

Chinnakrishnan Ballapuram, Kiran Puttaswamy, Gabriel H. Loh, Hsien-Hsin S. Lee
2006 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems - CASES '06  
The Translation Look-aside Buffer (TLB), a content addressable memory, consumes significant power due to the associative search mechanism it uses in the virtual to physical address translation.  ...  Based on these two characteristics, we propose two techniques: an entropy-based speculative stack address TLB and a deterministic global address TLB to achieve energy reducing.  ...  To exploit these properties, we propose a novel Entropy based SPeculative -Translation Lookaside Buffer (ESP-TLB) mechanism for stack references, and an Entropy based DeTerministic -Translation Lookaside  ... 
doi:10.1145/1176760.1176797 dblp:conf/cases/BallapuramPLL06 fatcat:6x6y4bmkbng7znkz5tbjylu73u

Improving TLB energy for java applications on JVM

Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee
2008 2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation  
The TLB, a content addressable memory, can consume a significant power in these systems due to the nature of its associative search mechanism.  ...  In this paper, we propose and investigate three different optimizations for the TLB design, aiming to improve its power consumption for Java applications running on top of Java Virtual Machines.  ...  CONCLUSION In this paper, we investigate an energy-efficient Translation Lookaside Buffer (TLB) design for Java applications running on the JVM.  ... 
doi:10.1109/icsamos.2008.4664867 dblp:conf/samos/BallapuramL08 fatcat:4si2synh6va6hnrihqd6o5aaii

80μW/MHz 0.68V Ultra Low-Power Variation-Tolerant Superscalar Dual-Core Application Processor

Youngsu Kwon, Jae-Jin Lee, Kyoung-Seon Shin, Jin-Ho Han, Kyung-Jin Byun, Nak-Woong Eum
2015 IEIE Transactions on Smart Processing and Computing  
We propose implementation of a novel superscalar low-power processor core with a low supply voltage.  ...  The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of 80 W/MHz. The operating frequency of the core reaches 850MHz at 1.2V.  ...  The area of the core is 2.65mm 2 including all sub-cores, 32KB I$, 32KB D$, iTLB (instruction Translation Lookaside Bus), and dTLB (data address Translation Lookaside Bus).  ... 
doi:10.5573/ieiespc.2015.4.2.071 fatcat:72errhgvvzghhggpe5mkcnkfia

NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs

Azam Seyedi, Vasileios Karakostas, Stefan Cosemans, Adrian Cristal, Mario Nemirovsky, Osman Unsal
2015 Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15)  
As a use case for the NEMsCAM cell, we design first-level data and instruction Translation Lookaside Buffers (TLBs) with 16nm CMOS technology at 2GHz.  ...  The simulations show that the NEMsCAM TLB reduces the energy consumption per search operation (by 27%), write operation (by 41.9%) and standby mode (by 53.9%), and the area (by 40.5%) compared to a CMOSonly  ...  Translation Lookaside Buffer. A common employment of CAMs is in the TLB that holds recently used virtual-tophysical translations [19] . The processor searches the TLB on every memory operation.  ... 
doi:10.1109/nanoarch.2015.7180586 dblp:conf/nanoarch/SeyediKCCNU15 fatcat:kmxq4gqqpvcgvahgnrxppws2ym

Modular Synthesis of Heap Exploits

Dusan Repel, Johannes Kinder, Lorenzo Cavallaro
2017 Proceedings of the 2017 Workshop on Programming Languages and Analysis for Security - PLAS '17  
Recent efforts to automatically synthesize exploits for stack-based buffer overflows promise to help assess a vulnerability's severity more quickly and alleviate the burden of manual reasoning.  ...  While the appeal of such tools to potential attackers seems obvious, they actually offer a powerful pro-active defense strategy in the form of an automated penetration tester.  ...  Recall that S 2 E converts translation blocks that manipulate symbolic bytes into LLVM, for execution by KLEE.  ... 
doi:10.1145/3139337.3139346 dblp:conf/ccs/RepelKC17 fatcat:ch3dbqqotvbwjalfxw4jg5lmwy

Low-power cache organization through selective tag translation for embedded processors with virtual memory support

Xiangrong Zhou, Peter Petrov
2006 Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06  
By eliminating the need for address translation on cache access for the majority of references, a significant power reduction is achieved.  ...  Application knowledge regarding the nature of memory references is used to eliminate tag address translations for most of the cache accesses.  ...  The authors have proposed to replace the TLB with more scalable and power efficient Synonym Lookaside Buffer, as it stores only the current synonym instances.  ... 
doi:10.1145/1127908.1127999 dblp:conf/glvlsi/ZhouP06 fatcat:2zp2o7whdfexzcuty4llh5bwfm

The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches

Xiaogang Qiu, M. Dubois
2008 IEEE transactions on computers  
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB).  ...  The major idea is the replacement of the on-chip TLB by a synonym lookaside buffer (SLB).  ...  This dynamic translation is currently supported by a translation lookaside buffer (TLB), a cache for virtual-tophysical address translations.  ... 
doi:10.1109/tc.2008.108 fatcat:c6lyqm76njblhbqtukzfmsmtfq

Enhancement of Resource Scheduling on Gui Based Operating System

Ulfat Altaf, Deepinder Kaur
2022 International Journal of Scientific Research in Computer Science Engineering and Information Technology  
This approach differs from multiprocessing, as with multithreading processes & threads have to share resources of a single or multiple cores: computing units, CPU caches, & translation lookaside buffer  ...  CHALLENGES WITHIN RESEARCH Multiple threads could interfere with each other when sharing hardware resources such as caches or translation lookaside buffers (TLBs).  ...  A scheduler is what carries out scheduling activity.  ... 
doi:10.32628/cseit2176111 fatcat:eskc6ckjnjc7xm3es2xd6otz7e
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