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Reducing Resource Redundancy for Concurrent Error Detection Techniques in High Performance Microprocessors

S. Kumar, A. Aggarwal
The Twelfth International Symposium on High-Performance Computer Architecture, 2006.  
Redundant multi-threading (RMT) is an attractive approach for concurrent error detection and recovery.  ...  In this paper, we propose reducing resource redundancy as a means to mitigate the performance impact of redundancy.  ...  Background and Motivation Background In this paper, we consider a reliable microprocessor configuration running one redundant thread for concurrent error detection, shown in Figure 1 .  ... 
doi:10.1109/hpca.2006.1598130 dblp:conf/hpca/KumarA06 fatcat:teenvtxht5firebzrorjervbve

Improving Instruction Issue Bandwidth for Concurrent Error-Detecting Processors

Toshinori Sato, Akihiro Chiyonobu, Kazuki Joe
2006 Automated Software Engineering, IEEE International Conference  
In this paper, in order to reduce the performance penalty, we adopt RED into ROBbased microprocessors.  ...  Soft error tolerance is a hot research topic for modern microprocessors.  ...  Acknowledgements This work is partially supported by Grants-in-Aid for Scientific Research #16300019 and #176549 from Japan Society for the Promotion of Science. -10%  ... 
doi:10.1109/iwias.2006.27 fatcat:ftu3w2d2vfgmhcmsf4ouvhv2ja

Online BIST for embedded systems

H. Al-Asaad, B.T. Murray, J.P. Hayes
1998 IEEE Design & Test of Computers  
Embedded systems must meet increasingly high expectations of safety and high reliability. The authors survey onlinetesting techniques for identifying faults that can lead to system failure.  ...  Murray is a member of the technical staff of General Motors Global Research and Development Operations, where he has led projects in testing, high-dependability embedded systems, and computer architecture  ...  For example, the duplication-with-comparison (DWC) technique 5 detects any single error at the expense of 100% space redundancy.  ... 
doi:10.1109/54.735923 fatcat:j7xkxctuajdqhnxwhaev7r6ycy

Architectures for online error detection and recovery in multicore processors

D Gizopoulos, M Psarakis, S V Adve, P Ramachandran, S K S Hari, D Sorin, A Meixner, A Biswas, X Vera
2011 2011 Design, Automation & Test in Europe  
This paper focuses on dependable multicore processor architectures that integrate solutions for online error detection, diagnosis, recovery, and repair during field operation.  ...  It also describes in more detail three recently proposed effective architectural approaches: a software-anomaly detection technique (SWAT), a dynamic verification technique (Argus), and a core salvaging  ...  The abovementioned redundant execution approaches support concurrent error detection because redundant hardware (or software) runs concurrently with the normal one.  ... 
doi:10.1109/date.2011.5763096 dblp:conf/date/GizopoulosPARHSMBV11 fatcat:uli4r7onhrd5tatt4l2soy4pom

Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures [chapter]

Jie S. Hu, G. M. Link, Johnsy K. John, Shuai Wang, Sotirios G. Ziavras
2005 Lecture Notes in Computer Science  
In addition, our enhancements are compatible with many other proposed techniques, allowing for further performance improvement.  ...  Previously proposed instruction-level redundant execution, as a means of detecting errors, suffers from a severe performance loss due to the resource shortage caused by the large number of redundant instructions  ...  with concurrent error detection [12, 18, 11, 19, 4, 7] .  ... 
doi:10.1007/11572961_17 fatcat:owab4iwqd5alxcigdz3fi3uhma

Ultra low-cost defect protection for microprocessor pipelines

Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd Austin
2006 SIGARCH Computer Architecture News  
In case a failure is detected, we rely on the natural redundancy of instructionlevel parallel processors to repair the system so that it can still operate in a degraded performance mode.  ...  In this paper, we introduce a low-cost mechanism for tolerating a small number of silicon failures that occur in the field, i.e., while the device is in operation.  ...  We compared traditional defect tolerant mechanisms such as triple modular redundancy and error corrections codes with domain-specific techniques that include end-to-end error detection, resource sparing  ... 
doi:10.1145/1168919.1168868 fatcat:735im5zajzbpxcsyijynplvdwq

Ultra low-cost defect protection for microprocessor pipelines

Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd Austin
2006 Proceedings of the 12th international conference on Architectural support for programming languages and operating systems - ASPLOS-XII  
In case a failure is detected, we rely on the natural redundancy of instructionlevel parallel processors to repair the system so that it can still operate in a degraded performance mode.  ...  In this paper, we introduce a low-cost mechanism for tolerating a small number of silicon failures that occur in the field, i.e., while the device is in operation.  ...  We compared traditional defect tolerant mechanisms such as triple modular redundancy and error corrections codes with domain-specific techniques that include end-to-end error detection, resource sparing  ... 
doi:10.1145/1168857.1168868 dblp:conf/asplos/ShyamCPBA06 fatcat:hcqq4pai5ngjni6rbi4nukad3m

Ultra low-cost defect protection for microprocessor pipelines

Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd Austin
2006 ACM SIGOPS Operating Systems Review  
In case a failure is detected, we rely on the natural redundancy of instructionlevel parallel processors to repair the system so that it can still operate in a degraded performance mode.  ...  In this paper, we introduce a low-cost mechanism for tolerating a small number of silicon failures that occur in the field, i.e., while the device is in operation.  ...  We compared traditional defect tolerant mechanisms such as triple modular redundancy and error corrections codes with domain-specific techniques that include end-to-end error detection, resource sparing  ... 
doi:10.1145/1168917.1168868 fatcat:6nm2os5525aapmbhgxhg3ceopi

Ultra low-cost defect protection for microprocessor pipelines

Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd Austin
2006 SIGPLAN notices  
In case a failure is detected, we rely on the natural redundancy of instructionlevel parallel processors to repair the system so that it can still operate in a degraded performance mode.  ...  In this paper, we introduce a low-cost mechanism for tolerating a small number of silicon failures that occur in the field, i.e., while the device is in operation.  ...  We compared traditional defect tolerant mechanisms such as triple modular redundancy and error corrections codes with domain-specific techniques that include end-to-end error detection, resource sparing  ... 
doi:10.1145/1168918.1168868 fatcat:kqpadu2enzhhpihpxbztyvw73q

Toward systematic design of fault-tolerant systems

A. Avizienis
1997 Computer  
After 30 years of study and practice in fault tolerance, high-confidence computing remains a costly privilege of several critical applications.  ...  It is time to explore ways to deliver high-confidence computing to all users Algirdas Avizienis  ...  Yutao He contributed valuable assistance in the survey of microprocessors and in the preparation of this text.  ... 
doi:10.1109/2.585154 fatcat:z5wsbzr3frf7reeug2ce6kdqqy

Online diagnosis of hard faults in microprocessors

Fred A. Bower, Daniel J. Sorin, Sule Ozev
2007 ACM Transactions on Architecture and Code Optimization (TACO)  
In our reliable microprocessor design, we use DIVA dynamic verification to detect and correct errors.  ...  We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field faults, by leveraging existing microprocessor redundancy.  ...  ACKNOWLEDGMENTS We thank Alvy Lebeck and the rest of the Duke Architecture Reading Group for helpful feedback on this paper.  ... 
doi:10.1145/1250727.1250728 fatcat:lq2g3lffebaatixrm7rmycqdbe

Commercial fault tolerance: a tale of two systems

W. Bartlett, L. Spainhower
2004 IEEE Transactions on Dependable and Secure Computing  
There were and still are many similarities in the design philosophies of the two lines, including the use of redundant components and extensive error checking.  ...  The requirement for the original S/360 line was for very high availability; the requirement for the NonStop platform was for single fault tolerance against unplanned outages.  ...  To reduce human errors during concurrent card replacement, a group of LED indicators, one for each card position, is used to positively identify the card to be replaced.  ... 
doi:10.1109/tdsc.2004.4 fatcat:g5ht4nlexrdjtmpka2tjcai6fa

Prioritizing verification via value-based correctness criticality

Joonhyuk Yoo, Manoj Franklin
2007 2007 25th International Conference on Computer Design  
However, such a full re-execution significantly increases the demand on the processor resources, resulting in severe performance degradation.  ...  Microprocessors are becoming increasingly susceptible to soft errors due to the current trends of semiconductor technology scaling.  ...  workload for high performance fault-tolerant microprocessors.  ... 
doi:10.1109/iccd.2007.4601921 dblp:conf/iccd/YooF07 fatcat:mbedrvsu6rb7hoeahvzucj6jb4

Low-Cost Protection for SER Upsets and Silicon Defects

Mojtaba Mehrara, Mona Attariyan, Smitha Shyam, Kypros Constantinides, Valeria Bertacco, Todd Austin
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
In this paper we present a low-cost technique to harden a microprocessor pipeline and caches against these reliability threats.  ...  By utilizing low-cost techniques to address defects and SER, we keep protection costs significantly lower than traditional fault-tolerance approaches while providing high levels of coverage for a wide  ...  In contrast to traditional techniques, the design presented here leverages domain-specific fault-tolerance techniques that significantly reduce the performance and area overheads of providing high-coverage  ... 
doi:10.1109/date.2007.364449 fatcat:3w6pm3mygzegjmgnjn54ijarwq

Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

I. Herrera-Alzu, M. Lopez-Vallejo
2013 IEEE Transactions on Nuclear Science  
This characteristic, together with their high performance and high logic density, proves to be very convenient for a number of ground and space level applications.  ...  This is a first order concern for applications in harsh radiation environments, and starts to be a concern for high reliability ground applications.  ...  In addition, architectural improvements in this device, such as built-in Error Detection and Correction (EDAC) for BRAM and SET filters for flip-flops, allow reducing A-Layer upsets significantly.  ... 
doi:10.1109/tns.2012.2231881 fatcat:y34el2up7nhvzbrhecksrkogri
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