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Fault tolerant communication in 3D integrated systems

Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi
<span title="">2010</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/64vpoz5fx5azda553iibjuf7h4" style="color: black;">2010 International Conference on Dependable Systems and Networks Workshops (DSN-W)</a> </i> &nbsp;
Connect layers with Thru-Silicon Vias (TSV) • Replace long (~mm) global 2D interconnects with shorter (~10s µm) TSV » Reduce RC delays » Reduce power dissipation 3D Integration and Systems-on-Chip SoC  ...  • Area overhead ~30% » Extra coding / detection / correction modules » More spares for targeted yield Increases defect probability • More spares • Area OH » ~300% Link Dissipated Power  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/dsnw.2010.5542606">doi:10.1109/dsnw.2010.5542606</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/dsn/PascaAB10.html">dblp:conf/dsn/PascaAB10</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/23ms2yfzufhvzhwlezcjoqe5zi">fatcat:23ms2yfzufhvzhwlezcjoqe5zi</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170808225112/http://webhost.laas.fr/TSF/WDSN10/WDSN10_files/Slides/WDSN10_Pasca.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/09/f1/09f1aa3cac3a6e6761d485581ff5b552cbf269a1.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/dsnw.2010.5542606"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions

Swarup Bhunia, Kaushik Roy
<span title="">2007</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/c6t4qycpy5haxkpjvywsoox6dq" style="color: black;">2007 IEEE International Test Conference</a> </i> &nbsp;
high yield while achieving low power dissipation.  ...  Numerous design techniques have been investigated for both logic and memory circuits to address the growing issues with power and variations.  ...  ) has been extremely effective in reducing the power dissipation.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/test.2007.4437659">doi:10.1109/test.2007.4437659</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/itc/BhuniaR07.html">dblp:conf/itc/BhuniaR07</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/bdsfonjkkrhnxeigu3gog4y6de">fatcat:bdsfonjkkrhnxeigu3gog4y6de</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170810220234/http://www.csee.usf.edu/~swaroopghosh/paper/ITC2008.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/c0/ac/c0ac3396cdf73abff03cb32cfabacd3c079da962.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/test.2007.4437659"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Biologically Inspired Robust Tera-Device Processors

Michael Nicolaidis
<span title="">2012</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/hkpx3vsnhrfb7jh6hlwads7olq" style="color: black;">IEEE Design &amp; Test of Computers</a> </i> &nbsp;
Low hardware cost principles In Cells, schemes implemented in hardware include repair and ECC for memories, repair and CED for interconnects, and CED for logic.  ...  Principles of high reliability While conventional massive-redundancy-based fault tolerance techniques do not work for high defect densities despite their high area and power penalties, Cells copes with  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mdt.2012.2211174">doi:10.1109/mdt.2012.2211174</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/rfl2pmrkrbgpbgetykpgz5brxi">fatcat:rfl2pmrkrbgpbgetykpgz5brxi</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180724054314/https://ieeexplore.ieee.org/ielx5/54/6416044/06257511.pdf?tp=&amp;arnumber=6257511&amp;isnumber=6416044" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/bd/d0/bdd00f218e5715b33302a7b1bf92ff5e974bc098.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mdt.2012.2211174"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Hierarchical fault tolerance memory architecture with 3-dimension interconnect

Da Wang, Yuanjiang Xie, Yu Hu, Huawei Li, Xiaowei Li
<span title="">2007</span> <i title="IEEE"> TENCON 2007 - 2007 IEEE Region 10 Conference </i> &nbsp;
For a memory with 1% bit-level failure rate and 50% device-level defect density, the proposed method can gain 100% reliability by using less than 30% extra overhead.  ...  This paper proposed hierarchical fault tolerance techniques for ultrahigh-density memories based on 3dimension interconnect technology.  ...  high defect density.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tencon.2007.4428893">doi:10.1109/tencon.2007.4428893</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/3r43f46z6rdpvo6uhdrvjimv44">fatcat:3r43f46z6rdpvo6uhdrvjimv44</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170809231600/http://sourcedb.cas.cn/sourcedb_ict_cas/cn/ictthesis/200907/P020090722624385941968.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/92/c8/92c899836f719e53cf332b19138a5489e4208cdb.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tencon.2007.4428893"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

LOW POWER AND IMPROVED SPEED 1T DRAM USING DYNAMIC LOGIC

T. NIRMALRAJ, S. K. PANDIYAN, C. SENTHILPARI
<span title="">2018</span> <i title="Taylor&#39;s University"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/3vxazte2xfh4vfhg6itjiodlsq" style="color: black;">Journal of Engineering Science and Technology</a> </i> &nbsp;
Our proposed and designed circuit gives better results in terms of power dissipation, speed, and Area.  ...  The new trend of the DRAM design is to characterize by its reliability, delay, low power dissipation, and area.  ...  The designed and proposed 3T DRAM is universally used by the advanced processor for on-chip data and program memory due to its high density and low cost of memory.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://doaj.org/article/a07d54005daa4a408006f5dd12809c7a">doaj:a07d54005daa4a408006f5dd12809c7a</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/zxyqkadi6nfdzlaaulbmgckzie">fatcat:zxyqkadi6nfdzlaaulbmgckzie</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20190214132255/http://jestec.taylors.edu.my:80/Vol%2013%20issue%206%20June%202018/13_6_18.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/ce/0c/ce0c002a2edc8be0f4ff975a48013b29feb3decb.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a>

Virtualization Based Efficient TSV Repair for 3-D Integrated Circuits

Muhammad Imran, Hyunseung Han, Jooho Kim, Taehyun Kwon, Jaeyong Chung, Joon-Sung Yang
<span title="">2019</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/q7qi7j4ckfac7ehf3mjbso4hne" style="color: black;">IEEE Access</a> </i> &nbsp;
It makes efficient use of the TSV redundancies in repairing the faulty TSVs. With less number of spare TSVs, the proposed architecture can reduce the area overhead by more than 70%.  ...  Reduction in the TSV count allows greater interconnect density and helps to mitigate the TSV-induced noise and stresses.  ...  INTRODUCTION Semiconductor device scaling is aimed at performance enhancement by reducing the interconnect delays, increasing density and decreasing power dissipation [1] .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/access.2019.2940211">doi:10.1109/access.2019.2940211</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/76mab2l2cjhmtdnydhvmg6kfii">fatcat:76mab2l2cjhmtdnydhvmg6kfii</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20201108062323/https://ieeexplore.ieee.org/ielx7/6287639/8948470/08832259.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/b8/7c/b87c7c0101dd49dd243820cc160f8c775c92b7dd.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/access.2019.2940211"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> ieee.com </button> </a>

Prospects for terabit-scale nanoelectronic memories

Dmitri B Strukov, Konstantin K Likharev
<span title="2004-12-11">2004</span> <i title="IOP Publishing"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/dtyhvneiqnak7lq5kh2hd4cjme" style="color: black;">Nanotechnology</a> </i> &nbsp;
For the simple "Repair Most" technique of bad bit exclusion, complemented with the Hamming-code error correction, these numbers are close to 2% and 0.1%, respectively.  ...  useful bit density if the fraction of bad nanodevices is below ~15%, while in order to get an order-of-magnitude advantage in density, the number of bad devices has to be decreased to ~2%.  ...  unacceptable power dissipation or memory access slowdown.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1088/0957-4484/16/1/028">doi:10.1088/0957-4484/16/1/028</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/a4aexdh2yvgabc56baop5dg4te">fatcat:a4aexdh2yvgabc56baop5dg4te</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20040808023254/http://rsfq1.physics.sunysb.edu:80/~likharev/nano/Memory04.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/e6/0d/e60d8aac57ab5486541e944bbcc61c40e872c658.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1088/0957-4484/16/1/028"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> iop.org </button> </a>

Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer

Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Tahoori
<span title="">2016</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/6nxn3oxzcveorfagbcbilem2ay" style="color: black;">2016 Euromicro Conference on Digital System Design (DSD)</a> </i> &nbsp;
The proposed methodology implements both arithmetic and memory elements, necessitated by achieving a computer, by considering performance parameters such as area, delay, power dissipation, and reliability  ...  In the last decade, several emerging technologies have been proposed and the time has come for studying new adhoc techniques and tools for logic synthesis, physical design and testing.  ...  parameters including reliability, area, delay, and power dissipation.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/dsd.2016.45">doi:10.1109/dsd.2016.45</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/dsd/AlexandrescuAAB16.html">dblp:conf/dsd/AlexandrescuAAB16</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/uuimqmkbhrhn7moetyaja5v5hq">fatcat:uuimqmkbhrhn7moetyaja5v5hq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200307041151/https://polen.itu.edu.tr/bitstream/11527/18004/1/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/4a/d6/4ad6db6375902fdc13185c524fcdc4123ad3b3a6.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/dsd.2016.45"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Stack up your chips: Betting on 3D integration to augment Moore's Law scaling [article]

Saurabh Sinha, Xiaoqing Xu, Mudit Bhargava, Shidhartha Das, Brian Cline, Greg Yeric
<span title="2020-05-21">2020</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>
In this talk, we will discuss some key challenges associated with 3D design and how design-for-3D will require us to break traditional silos of micro-architecture, circuit/physical design and manufacturing  ...  , power and cost but the actual magnitude of gains varies depending on end-application, technology choices and design.  ...  The primary yield improvement in monolithic 3D comes from the fact that the critical area for defect densities can be reduced by approximately 2X in monolithic 3D wafer processing.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/2005.10866v1">arXiv:2005.10866v1</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/3o32jrvjsjamffta4le7p4hxwi">fatcat:3o32jrvjsjamffta4le7p4hxwi</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200526011325/https://arxiv.org/pdf/2005.10866v1.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] </button> </a> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/2005.10866v1" title="arxiv.org access"> <button class="ui compact blue labeled icon button serp-button"> <i class="file alternate outline icon"></i> arxiv.org </button> </a>

3-D Data Storage, Power Delivery, and RF/Optical Transceiver—Case Studies of 3-D Integration From System Design Perspectives

Tong Zhang, Rino Micheloni, Guoyan Zhang, Zhaoran Rena Huang, James Jian-Qiang Lu
<span title="">2009</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/yfvtieuumfamvmjlc255uckdlm" style="color: black;">Proceedings of the IEEE</a> </i> &nbsp;
., solid-state data storage, power delivery, and hybrid radio-frequency/optical transceiver for distributed sensor networks, this paper intends to exemplify the potentials of exploiting the benefits of  ...  Three-dimensional (3-D) integration of systems by vertically stacking and interconnecting multiple materials, technologies, and functional components offers a wide range of benefits, including speed, bandwidth and density  ...  In general, all 3-D integration technologies would offer high-density component integration with small form factor (small size and light weight), reduced packaging, and reduced power (fewer I/Os to be  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/jproc.2008.2007478">doi:10.1109/jproc.2008.2007478</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/jteadadugzftnmpubdl4shygxu">fatcat:jteadadugzftnmpubdl4shygxu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170809094545/https://ecse.rpi.edu/~tzhang/pub/Proceeding3D09.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/7f/59/7f59866094fa903d8064cc5ed0a4da05337c1cc8.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/jproc.2008.2007478"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

CMOS IC Technology Scaling and Its Impact on Burn-In

A. Vassighi, O. Semenov, M. Sachdev, A. Keshavarzi, C. Hawkins
<span title="">2004</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/iyo2h57exjczrg3z6tru76uliu" style="color: black;">IEEE transactions on device and materials reliability</a> </i> &nbsp;
Burn-in is a quality improvement procedure challenged by the high leakage currents that are rapidly increasing with IC technology scaling.  ...  This article describes how CMOS IC technology scaling impacts semiconductor burn-in and burn-in procedures.  ...  INTRODUCTION T RANSISTOR scaling is the primary factor in achieving high-performance microprocessors and memories.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tdmr.2004.826591">doi:10.1109/tdmr.2004.826591</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/v3acbhskxrawfcgeas5ru7t26m">fatcat:v3acbhskxrawfcgeas5ru7t26m</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20050225184100/http://www.ece.uwaterloo.ca:80/%7Ecdr/pubs/vassighi.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/ec/94/ec94a27b576a69e41f393747042dfb989146a39b.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tdmr.2004.826591"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Logic synthesis and testing techniques for switching nano-crossbar arrays

Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Tahoori
<span title="">2017</span> <i title="Elsevier BV"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/brvj2ugukfgvhevdy5lwzvdy6m" style="color: black;">Microprocessors and microsystems</a> </i> &nbsp;
The proposed methodology implements logic, arithmetic, and memory elements by considering performance parameters such as area, delay, power dissipation, and reliability.  ...  In the last decade, several emerging technologies have been proposed and the time has come for studying new ad-hoc techniques and tools for logic synthesis, physical design and testing.  ...  functional with faulty spare units (in case of a high defect density) to create a fault-free unit.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1016/j.micpro.2017.08.004">doi:10.1016/j.micpro.2017.08.004</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/rapt2rcyljf3li3zgl2flyenqu">fatcat:rapt2rcyljf3li3zgl2flyenqu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200307060220/https://polen.itu.edu.tr/bitstream/11527/18002/1/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/9c/ba/9cba60893c2ca291b72068771d066caf14c02732.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1016/j.micpro.2017.08.004"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> elsevier.com </button> </a>

Process Variations and Process-Tolerant Design

Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
<span title="">2007</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/xvg6rzbspbbfnhjy5l46rz45f4" style="color: black;">20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID&#39;07)</a> </i> &nbsp;
Variations in the device parameters, both systematic and random, translate into variations in circuit parameters like delay and leakage power, leading to loss in parametric yield.  ...  and memory.  ...  Due to quadratic dependence of dynamic power of a circuit on its operating voltage, supply voltage scaling has been extremely effective in reducing the power dissipation.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/vlsid.2007.131">doi:10.1109/vlsid.2007.131</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/vlsid/BhuniaMR07.html">dblp:conf/vlsid/BhuniaMR07</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/haw2cidqhng7ngucgvwiftnsza">fatcat:haw2cidqhng7ngucgvwiftnsza</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20171025113152/http://swarup.ece.ufl.edu:80/papers/IC/IC10.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/cf/ad/cfad18b78d525a716fce13dbb3680e83ac7cf796.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/vlsid.2007.131"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Itanium 2 processor 6M: higher frequency and larger L3 cache

S. Rusu, H. Muljono, B. Cherkauer
<span title="">2004</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/gvjkwgwwvnakpbfssxpqjozbqm" style="color: black;">IEEE Micro</a> </i> &nbsp;
The worst-case power dissipation is 130 W, although the power dissipation on a typical server work-load is 107 W.  ...  At the same time, we had to limit the power dissipation to fit into the existing platform envelope.  ...  Given the large on-die cache, both of these features increase the ability to identify and repair defects.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mm.2004.1289279">doi:10.1109/mm.2004.1289279</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/zk6jlt3cavd5hjfo35j6je5faq">fatcat:zk6jlt3cavd5hjfo35j6je5faq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170809034532/http://home.deib.polimi.it/silvano/FilePDF/ARC-MULTIMEDIA/ItaniumII_IEEEMicro2004.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/86/7a/867ac23cd2e5ab8924aa664d9b75c9f2e753574f.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mm.2004.1289279"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Error tolerance

A.B. Kahng
<span title="">2003</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/hkpx3vsnhrfb7jh6hlwads7olq" style="color: black;">IEEE Design &amp; Test of Computers</a> </i> &nbsp;
Methodology for the former is increasingly costly in terms of guard banding, and methodology for the latter is still under development.  ...  THE INTERNATIONAL Technology Roadmap for Semiconductors (ITRS) states that error tolerance is a future "cross-cutting challenge" for design and test.  ...  This is bad news for analog and low-power designs. I Joule heating occurs because higher clock frequencies cause faster charge transfers, which in turn increase collisions and energy dissipation.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mdt.2003.1173057">doi:10.1109/mdt.2003.1173057</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/xqpilusdyvh3ppqgv4wcfhms3q">fatcat:xqpilusdyvh3ppqgv4wcfhms3q</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20060103004426/http://vlsicad.ucsd.edu:80/Publications/Columns/column6.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/e9/26/e9266fd6123b2e490ebd8eda6df8c9df50a50513.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mdt.2003.1173057"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>
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