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Clean-Prefetcher: Look-Ahead Prefetching without Cache Pollution

Minshin Cho, Jae Young Hur, Wooyoung Jang
2021 IEICE Electronics Express  
storing instructions in undetermined paths via refreshing DRAM cells.  ...  The DRAM cells highly charged will be quickly accessed.  ...  After the charge sharing operation, the sensing and restoring speed of the fully charged DRAM cell is faster than that of the partially charged DRAM cell.  ... 
doi:10.1587/elex.18.20210027 fatcat:3qwyca6quzdufkm4awguxfk4vq

Application driven network-on-chip architecture exploration & refinement for a complex SoC

Jean-Jacques Lecler, Gilles Baillieu
2011 Design automation for embedded systems  
As the controller, it must be aware of the DRAM penalties in order to select adequate patterns.  ...  As stated earlier, the DRAM scheduler is in charge of interleaving the requests before sending them to the controller.  ... 
doi:10.1007/s10617-011-9075-5 fatcat:m6tuyuj37babdgdorie6hchzge

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

Prateek Shantharama, Akhilesh S. Thyagaturu, Martin Reisslein
2020 IEEE Access  
[266] have comprehensively investigated the DRAM access latency components, which are: i) activation, ii) precharge, and iii) restoration.  ...  MEMORY 1) DRAM Understanding the latency components of DRAM memory accesses facilitates the effective design of NF applications to exploit the locality of data within DRAM system memory with reduced latency  ... 
doi:10.1109/access.2020.3008250 fatcat:kv4znpypqbatfk2m3lpzvzb2nu

Memory leads the way to better computing

H.-S. Philip Wong, Sayeef Salahuddin
2015 Nature Nanotechnology  
Embedded DRAM, Fast Cycle DRAM and Reduced Latency DRAM all demonstrate fast DRAM devices. However, all of these carry a substantial die size penalty.  ...  An intermediate level of non-volatile memory -with latency, bandwidth, and cost/bit between DRAM and disk would be valuable to reduce the latency of the checkpoint operation and speed access to frequently  ... 
doi:10.1038/nnano.2015.29 pmid:25740127 fatcat:d6iiuuwcozbxlgn4kxxzdzwd4m

Eurolab-4-HPC Long-Term Vision on High-Performance Computing [article]

Theo Ungerer, Paul Carpenter
2018 arXiv   pre-print
A passive interposer, often implemented with an organic material to reduce cost, provides multiple levels of metal interconnects and vertical vias for inter-chiplet connectivity and for redistribution  ...  However, more and more hardware devices will use 3D technology, so even system-level design will need to become 3D-aware.  ... 
arXiv:1807.04521v1 fatcat:5neetrgubjhnvcajcktpkohrzq

Energy-aware lossless data compression

Kenneth C. Barr, Krste Asanović
2006 ACM Transactions on Computer Systems  
It can therefore be beneficial to perform additional computation to reduce the number of bits transmitted.  ...  One such energy-aware suggestion is asymmetric compression, the use of one compression algorithm on the transmit side and a different algorithm for the receive path.  ...  We begin by looking at the number of instructions each requires to remove and restore a bit (Table V) .  ... 
doi:10.1145/1151690.1151692 fatcat:x22sj3wugbbqzfcgpksq2ndkai

Energy aware lossless data compression

Kenneth Barr, Krste Asanović
2003 Proceedings of the 1st international conference on Mobile systems, applications and services - MobiSys '03  
It can therefore be beneficial to perform additional computation to reduce the number of bits transmitted.  ...  One such energy-aware suggestion is asymmetric compression, the use of one compression algorithm on the transmit side and a different algorithm for the receive path.  ...  We begin by looking at the number of instructions each requires to remove and restore a bit (Table V) .  ... 
doi:10.1145/1066116.1066123 fatcat:unyoxuspt5g37abrgzbm2juyge

Controlling Energy Demand in Mobile Computing Systems

Carla Schlatter Ellis
2007 Synthesis Lectures on Mobile and Pervasive Computing  
For example, the look-ahead algorithm based on EDF (Pillai and Shin 2001) plans in reverse EDF order to defer work as late as possible in the schedule (betting that it will not be needed), thus reducing  ...  Another trend is society's growing awareness of the role of energy in climate change. Energy conservation will become a higher priority as we look for ways to reduce the size of our carbon footprint.  ... 
doi:10.2200/s00089ed1v01y200704mpc002 fatcat:myednkwcj5h5jizajmmhrj6hmy

Addressing failures in exascale computing

Marc Snir, Robert W Wisniewski, Jacob A Abraham, Sarita V Adve, Saurabh Bagchi, Pavan Balaji, Jim Belak, Pradip Bose, Franck Cappello, Bill Carlson, Andrew A Chien, Paul Coteus (+16 others)
2014 The international journal of high performance computing applications  
Therefore, we considered the following three design points: (1) business as usual, (2) system-level resilience, and (3) application-level resilience.  ...  The time to restart (which includes the time to restore the system to a consistent state) is MTBF; 3.  ...  reconfiguration (via updates in the routing tables, etc.).  ... 
doi:10.1177/1094342014522573 fatcat:menonpmgdfflzamz2fsivevxqm

A Survey of Big Data Machine Learning Applications Optimization in Cloud Data Centers and Networks [article]

Sanaa Hamid Mohamed, Taisir E.H. El-Gorashi, Jaafar M.H. Elmirghani
2019 arXiv   pre-print
Moreover, enterprises with multiple tenants requesting various big data services are challenged by the need to optimize leasing their resources at reduced running costs and power consumption while avoiding  ...  However, the increasing traffic between and within the data centers that migrate, store, and process big data, is becoming a bottleneck that calls for enhanced infrastructures capable of reducing the congestion  ...  Such transfers are typically free of charge within the same geographical zone to promote the use of both services, but are charged if carried between different zones.  ... 
arXiv:1910.00731v1 fatcat:kvi3br4iwzg3bi7fifpgyly7m4

Software-based Microarchitectural Attacks [article]

Daniel Gruss
2017 arXiv   pre-print
We present a generic attack to infer the translation level for every virtual address to defeat ASLR. 3.  ...  We present two generic attack primitives leveraging the prefetch instructions: the translation-level oracle and the address-translation oracle.  ...  DRAM is volatile memory and discharges over time. The refresh interval defines when the cell charge is read and restored to sustain the value.  ... 
arXiv:1706.05973v1 fatcat:4hwdpe4dancmblsxasg3a75h7a

Co-processor-based Behavior Monitoring

Ronny Chevalier, Maugan Villatel, David Plaquin, Guillaume Hiet
2017 Proceedings of the 33rd Annual Computer Security Applications Conference on - ACSAC 2017  
The CFG needs to be defined ahead of time and it can be computed via source code analysis [1] , binary analysis [80] , or execution profiling [76] .  ...  (CC4) Low latency Sending a message should be fast (e.g., sub-microsecond), because low-level components need to minimize the time spent performing their task to avoid impacting higher-level components  ... 
doi:10.1145/3134600.3134622 dblp:conf/acsac/ChevalierVPH17 fatcat:jizvvr647rgmpfbvc7xp7x7rsu

Microkernel Mechanisms for Improving the Trustworthiness of Commodity Hardware

Yanyan Shen, Kevin Elphinstone
2015 2015 11th European Dependable Computing Conference (EDCC)  
kernel mechanisms, fingerprint validation and kernel barrier timeout, detecting fault-induced execution divergences between the replicated systems, with the flexibility of tuning the error detection latency  ...  Summary and Looking Forward We can only see a short distance ahead, but we can see plenty there that needs to be done.  ...  The SER performance of DRAM cells is improving as technology advances [Baumann, 2003; Slayman, 2011] : over seven generations, the SER of DRAM has been reduced by more than 1000 times [Baumann, 2005b  ... 
doi:10.1109/edcc.2015.16 dblp:conf/edcc/ShenE15 fatcat:xq65e72x7zcnjbbmrwpgebqnxa

Dependable embedded systems

2008 2008 6th IEEE International Conference on Industrial Informatics  
For example, shall arithmetic adders follow a ripple-carry or carry-look-ahead architecture (enumerative decision)? What technology node to choose (discrete decision)?  ...  It increases performance by reducing the inter-thread communication latency.  ...  Uncertainty-Aware Compositional System-Level Reliability Analysis It should be noted that, for the sake of improving the accuracy of the experiments, all of the simulation results were retrieved after  ... 
doi:10.1109/indin.2008.4618103 fatcat:hal6brsgsjg5rlo3u5xil46pxi

Multiprocessor Real-Time Locking Protocols: A Systematic Review [article]

Björn B. Brandenburg
2019 arXiv   pre-print
A special focus is placed on the suspension-oblivious and suspension-aware analysis approaches for semaphore protocols, their respective notions of priority inversion, optimality criteria, lower bounds  ...  s second algorithm restores the local-spin property Multicore platforms also often feature hardware-managed, implicitly shared resources such as last-level caches (LLCs), memory controllers, DRAM  ...  In the absence of nesting, this reduces again to FIFO queues, but when issuing nested requests, jobs may benefit from an earlier timestamp and "skip ahead" of jobs that acquired their tokens at a later  ... 
arXiv:1909.09600v1 fatcat:tmqcpiuxfbbd5jrcecgvoeanpm
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