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Reducing Branch Misprediction Penalty via Selective Branch Recovery

A. Gandhi, H. Akkary, S.T. Srinivasan
10th International Symposium on High Performance Computer Architecture (HPCA'04)  
In this paper, we propose a novel method, called Selective Branch Recovery (SBR), to reduce both components of branch misprediction penalty.  ...  Thus, SBR addresses both components of branch misprediction penalty.  ...  In this paper, we propose Selective Branch Recovery (SBR) to reduce branch misprediction penalty.  ... 
doi:10.1109/hpca.2004.10004 dblp:conf/hpca/GandhiAS04 fatcat:ca435at6lzfmln6ewv6iupvru4

Transparent control independence (TCI)

Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham H. Akkary
2007 Proceedings of the 34th annual international symposium on Computer architecture - ISCA '07  
Superscalar architectures have been proposed that exploit control independence, reducing the performance penalty of branch mispredictions by preserving the work of future misprediction-independent instructions  ...  When the mispredicted branch resolves, recovery is achieved by fetching the self-sufficient, condensed recovery program.  ...  This penalty can be reduced at the expense of reduced branch coverage, using branch confidence.  ... 
doi:10.1145/1250662.1250717 dblp:conf/isca/Al-ZawawiRRA07 fatcat:yhnymgwllvbkfnegvjv4vzc5fu

Hardware Efficient Piecewise Linear Branch Predictor

Jiajin Tu, Jian Chen, Lizy John
2007 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)  
This paper presents two novel techniques targeting at reducing the hardware cost of the predictor, i.e., history skewed indexing and stack-based misprediction recovery.  ...  recover predictor states from misprediction.  ...  In other words, stack based misprediction recovery could increase the branch misprediction penalty and lead to degradation of instruction-per-cycle (IPC) rate.  ... 
doi:10.1109/vlsid.2007.89 dblp:conf/vlsid/TuCJ07 fatcat:jez3bpey6zaf3nziigqo4k262y

Transparent control independence (TCI)

Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham H. Akkary
2007 SIGARCH Computer Architecture News  
Superscalar architectures have been proposed that exploit control independence, reducing the performance penalty of branch mispredictions by preserving the work of future mispredictionindependent instructions  ...  When the mispredicted branch resolves, recovery is achieved by fetching the self-sufficient, condensed recovery program.  ...  Thus, recovery is more selective and this reduces misprediction penalties. Specifically, the work of misprediction-independent instructions (CIDI) is saved.  ... 
doi:10.1145/1273440.1250717 fatcat:gxaouga5t5hhdiaghj65xjncyu

Modeling value speculation: an optimal edge selection problem

Chao-ying Fu, J.T. Bodine, T.M. Conte
2003 IEEE transactions on computers  
In processor can accurately predict when to execute recovery code. The correct BNE branch prediction avoids the penalties for flushing pipeline stages in the case of branch misprediction.  ...  In the case of value misprediction, penalties are incurred for recovery. The total penalty for mispredicting node N; is denoted by Penalty(N;) and is described in Fig. 3.  ... 
doi:10.1109/tc.2003.1183944 fatcat:oqm6lhu2cffunn66scyc5v3cda

Predicate prediction for efficient out-of-order execution

Weihaw Chuang, Brad Calder
2003 Proceedings of the 17th annual international conference on Supercomputing - ICS '03  
We show that the penalty for mispredicting a predicate is not as severe as mispredicting a branch. Thus, making it advantageous to replace hard to predict branches with predicate predictions.  ...  We present a predicate misprediction recovery architecture that replays instructions through the renamer to link up the correct dependencies on a misprediction.  ...  However, the predicate misprediction penalty is not as severe as a branch misprediction.  ... 
doi:10.1145/782814.782840 dblp:conf/ics/ChuangC03 fatcat:demrdw43czdurcqquziygfyji4

Predicate prediction for efficient out-of-order execution

Weihaw Chuang, Brad Calder
2003 Proceedings of the 17th annual international conference on Supercomputing - ICS '03  
We show that the penalty for mispredicting a predicate is not as severe as mispredicting a branch. Thus, making it advantageous to replace hard to predict branches with predicate predictions.  ...  We present a predicate misprediction recovery architecture that replays instructions through the renamer to link up the correct dependencies on a misprediction.  ...  However, the predicate misprediction penalty is not as severe as a branch misprediction.  ... 
doi:10.1145/782837.782840 fatcat:dj43frlsubgotcczgcdo2434ie

Mower

Zhaoxiang Jin, Görkem Aşilioğlu, Soner Önder
2015 Proceedings of the 29th ACM on International Conference on Supercomputing - ICS '15  
Each of these tasks contribute to the branch misprediction penalty and each must be targeted individually to reduce its impact on processor performance.  ...  Mower helps to reclaim the invalid instructions early by which more energy is saved and misprediction penalty is reduced.  ... 
doi:10.1145/2751205.2751228 dblp:conf/ics/JinAO15 fatcat:qnz3bwfyuzaaxk23vav5ipkdk4

EOLE: Toward a Practical Implementation of Value Prediction

Arthur Perais, Andre Seznec
2015 IEEE Micro  
Pipeline squashing at execution time results in a minimum misprediction penalty similar to the branch misprediction penalty.  ...  Using pipeline squashing is straightforward, but costly as the minimum value misprediction penalty is the same as the minimum branch misprediction penalty.  ...  His research interests include microprocessor architecture including caches, branch predictors and all forms of speculative execution. André Seznec is an IEEE fellow.  ... 
doi:10.1109/mm.2015.45 fatcat:43av5cmoqjfy7gqilh3naozmsi

Register Indirect Jump Target Forwarding

Ryota SHIOYA, Naruki KURATA, Takashi TOYOSHIMA, Masahiro GOSHIMA, Shuichi SAKAI
2013 IEICE transactions on information and systems  
The prediction of the targets of register indirect jumps is more difficult than the prediction of the direction of conditional branches.  ...  Consequently, the branch misprediction penalty is not reduced than that in Fig. 6 .  ...  Static Code Scheduling Static code scheduling generally reduces branch misprediction penalties of virtual function calls.  ... 
doi:10.1587/transinf.e96.d.278 fatcat:gp5gu5yprnar5cqtrrnt4fhaom

BADGR: A practical GHR implementation for TAGE branch predictors

David J. Schlais, Mikko H. Lipasti
2016 2016 IEEE 34th International Conference on Computer Design (ICCD)  
In this work, we explore global history register (GHR) implementations for Tagged Geometric length (TAGE) style branch predictors with speculative updates.  ...  To reduce these inefficiencies, we introduce BADGR, a novel GHR design for TAGE predictors that lowers power consumption and chip area over naive checkpointing techniques by 90% and 85%, respectively.  ...  In this work, we show that zero and partial recovery leads to a large penalty in TAGE misprediction rates.  ... 
doi:10.1109/iccd.2016.7753338 dblp:conf/iccd/SchlaisL16 fatcat:f346la4fjrexlhopdhkfivvx7y

A study of control independence in superscalar processors

E. Rotenberg, Q. Jacobson, J. Smith
1999 Proceedings Fifth International Symposium on High-Performance Computer Architecture  
Even so, control independence can close the performance gap between real and perfect branch prediction by as much as half.  ...  The third approach is aimed at reducing the penalty after a misprediction occurs.  ...  Loads may proceed ahead of unresolved stores, and any memory hazards are detected as store addresses become available [12] --recovery is via the selective reissuing mechanism.  ... 
doi:10.1109/hpca.1999.744346 dblp:conf/hpca/RotenbergJS99 fatcat:ns45qyk5wzglnayipgcacseine

The performance potential of value and dependence prediction [chapter]

Mikko H. Lipasti, John P. Shen
1997 Lecture Notes in Computer Science  
These discoveries minimize the per-cycle instruction throughput (or IPC) penalty of deeper pipelining of instruction dispatch and result in average integer program speedups ranging from 22% to 106%, depending  ...  Fig. 1 . 1 Branch Misprediction Penalty.  ...  branch, while the MF snapshot corresponding to that branch is retrieved from the branch recovery stack.  ... 
doi:10.1007/bfb0002851 fatcat:nguhuzipfbcp7kylp6nfsezkoy

Checkpoint processing and recovery: an efficient, scalable alternative to reorder buffers

H. Akkary, R. Rajwar, S.T. Srinivasan
2003 IEEE Micro  
Mispredicting a non-checkpointed branch will force a recovery to a prior checkpoint.  ...  Because branch mispredicts are the most frequent cause of rename map table recovery, ideally, we would like to create checkpoints to recover processor state exactly at mispredicted branches.  ... 
doi:10.1109/mm.2003.1261382 fatcat:2mcoqyz4d5capi5vn7z5t3ixgi

Slipstream processors

Karthik Sundaramoorthy, Zach Purser, Eric Rotenberg
2000 SIGPLAN notices  
Mispredictions resulting from conventional speculation are detectable by the A-stream, do not corrupt the A-stream context, and do not involve the recovery controller.  ...  Conventional speculation occurs when branches are predicted and the branch-related computation has not been removed from the A-stream.  ...  AR-SMT runs the two programs simultaneously [37] but delayed (via the delay buffer), reducing the performance overhead of time redundancy.  ... 
doi:10.1145/356989.357013 fatcat:vs4txm2jsbhfzfegv3drxfo4c4
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