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*PHDD: an efficient graph representation for floating point circuit verification

Yimg-An Chen, Bryant
1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97  
The size of the graph to represent the IEEE floating point encoding is linear with the word size. The complexity of floating point multiplication grows linearly with the word size.  ...  Previous attempts at verifying floating point multipliers required manual intervention. We verified floating point multipliers before the rounding stage automatically.  ...  Figure 7 illustrates the *PHDD representation of floating point addition with two exponent bits for each floating point operand. Observe that the negation edge reduces the graph size by half.  ... 
doi:10.1109/iccad.1997.643251 dblp:conf/iccad/ChenB97 fatcat:s7qr5ao2e5e7pji7olz5iuso5y

Iterative solution of large, sparse linear systems on a static data flow architecture: Performance studies

Daniel A. Reed, Merrell L. Patrick
1985 IEEE transactions on computers  
Simi lar functions exist for the floating point and memory access delays at each graph step.  ...  steps in a cycle Μ number of matrix partitions Ν matrix dimension Ν, number of floating point units in a PE Ni number of logic units in a PE o, number of floating point operations/graph  ... 
doi:10.1109/tc.1985.6312190 fatcat:ck3jkp7iwvbmldhhay7fu556hy

A Log-Likelihood Ratio based Generalized Belief Propagation

Alexandru Amaricai, Mohsem Bahrami, Bane Vasic
2019 IEEE EUROCON 2019 -18th International Conference on Smart Technologies  
The key novelties of the proposed LLR-GBP are: (i) reduced fixed point precision for messages instead of computational complex floating point format, (ii) operations performed in logarithm domain, thus  ...  In this paper, we propose a reduced complexity Generalized Belief Propagation (GBP) that propagates messages in Log-Likelihood Ratio (LLR) domain.  ...  to the 64-bit floating point probabilistic GBP.  ... 
doi:10.1109/eurocon.2019.8861528 dblp:conf/eurocon/AmaricaiBV19 fatcat:c2ktx2z4jvdszgiuyqk7bx6gza

On the Computation of Correctly Rounded Sums

Peter Kornerup, Vincent Lefevre, Nicolas Louvet, Jean-Michel Muller
2012 IEEE transactions on computers  
In particular, we show that among the set of the algorithms with no comparisons performing only floating-point additions/subtractions, the 2Sum algorithm introduced by Knuth is minimal, both in terms of  ...  number of operations and depth of the dependency graph.  ...  Among all the algorithms that computes the same results as 2Sum, • each one requires at least 5 operations; • each one with 5 operations reduces to Mag2Sum; • each one has depth at least 3.  ... 
doi:10.1109/tc.2011.27 fatcat:adapgb6drjfalbg73f4c5ezfb4

On the Computation of Correctly-Rounded Sums

P. Kornerup, V. Lefevre, N. Louvet, J.M. Muller
2009 2009 19th IEEE Symposium on Computer Arithmetic  
In particular, we show that among the set of the algorithms with no comparisons performing only floating-point additions/subtractions, the 2Sum algorithm introduced by Knuth is minimal, both in terms of  ...  number of operations and depth of the dependency graph.  ...  Among all the algorithms that computes the same results as 2Sum, • each one requires at least 5 operations; • each one with 5 operations reduces to Mag2Sum; • each one has depth at least 3.  ... 
doi:10.1109/arith.2009.16 dblp:conf/arith/KornerupLLM09 fatcat:mifa3lcjcfb57ldg2mzmuga4tm

A register allocation framework based on hierarchical cyclic interval graphs [chapter]

Laurie J. Hendren, Guang R. Gao, Erik R. Altman, Chandrika Mukerji
1992 Lecture Notes in Computer Science  
Whenever possible, it favors register floats (moving values from one register to another) over the traditional register spills (storing a spilled variable into memory).  ...  In this paper, we present a new register allocation framework based on hierarchical cyclic interval graphs.  ...  Both benchmarks are also floating point intensive and use double precision (64bit) arithmetic. Hence we concentrate on the allocation and spilling of floating point registers.  ... 
doi:10.1007/3-540-55984-1_17 fatcat:mlli3y7ktvbrbjnyezb6muyzw4

A reduced-precision streaming SpMV architecture for Personalized PageRank on FPGA [article]

Alberto Parravicini, Francesco Sgherzi, Marco D. Santambrogio
2020 arXiv   pre-print
FPGAs provide quick execution times while offering precise control over the accuracy of the results thanks to reduced-precision fixed-point arithmetic.  ...  Our implementation achieves speedups up to 6x over a reference floating-point FPGA architecture and a state-of-the-art multi-threaded CPU implementation on 8 different data-sets, while preserving the numerical  ...  Results for synthetic graphs are averaged, as no difference was observed among distributions.  ... 
arXiv:2009.10443v1 fatcat:puzymxmb2zgath45zeikrn4sqa

Bi-GCN: Binary Graph Convolutional Network [article]

Junfu Wang, Yunhong Wang, Zhen Yang, Liang Yang, Yuanfang Guo
2021 arXiv   pre-print
Graph Neural Networks (GNNs) have achieved tremendous success in graph representation learning.  ...  According to the theoretical analysis, our Bi-GCN can reduce the memory consumption by an average of ~30x for both the network parameters and input data, and accelerate the inference speed by an average  ...  Therefore, the size of the parameters can be reduced by a factor of 2N d out floating-point multiplication operations. floating-point multiplication operations.  ... 
arXiv:2010.07565v2 fatcat:n44xyyej7beozb5w5bdnmq5gj4

Energy Efficient Acceleration Of Floating Point Applications Onto CGRA

Satyajit Das, Rohit Prasad, Kevin J. M. Martin, Philippe Coussy
2020 ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)  
In this paper, we propose a novel CGRA architecture and associated compilation flow supporting both integer and floating-point computations for energy efficient acceleration of DSP applications.  ...  For the floating point operation binding, the algorithm finds the binding solution only for the first operation node among all the dummy nodes (i.e. node 4 in Fig. 3 (b) ).  ...  To support floating point operations, we have employed floating point multiplier, adder/subtractor and divider/square-root units inside the PEs as shown in the Fig.2.  ... 
doi:10.1109/icassp40776.2020.9054613 dblp:conf/icassp/DasPMC20 fatcat:lbaxxoa3wvbwhmgi2arfnqqew4

A map-matching algorithm with low-frequency floating car data based on matching path

Ling Yuan, Dan Li, Song Hu
2018 EURASIP Journal on Wireless Communications and Networking  
ITS makes a new way of interaction among three main traffic systems: car, road, and traffic, which can reduce traffic congestion to improve the traffic capacity [2, 3].  ...  The proposed algorithm preprocesses the floating car data and road network data to determine the potential points and sections by constructing the error region.  ...  graph G T (V T , E T ) Division graph with a single potential point Yuan et al.  ... 
doi:10.1186/s13638-018-1154-x fatcat:efdofudy3nalbgmiffgeehvppi

Optimizing coarse-grained units in floating point hybrid FPGA

Chi Wai Yu, Alastair M. Smith, Wayne Luk, Philip H.W. Leong, Steven J.E. Wilton
2008 2008 International Conference on Field-Programmable Technology  
This paper introduces a novel methodology to optimize coarse-grained floating point units (FPUs) in a hybrid FPGA.  ...  We first study the area, speed and utilization trade-off of the selected FPU subgraphs in a set of floating point benchmark circuits.  ...  Common Subgraph Extraction Floating point applications have common characteristics for floating point computations.  ... 
doi:10.1109/fpt.2008.4762366 dblp:conf/fpt/YuSLLW08 fatcat:gk7dhmqpv5c5lkzbtfvfvrigmu

Editorial

Yuke Wang, Yu Hen Hu
2002 EURASIP Journal on Advances in Signal Processing  
The first paper proposes a lightweight floating point arithmetic, a family of customizable floating-point data formats, which bridges the design gap between software and hardware.  ...  The third paper introduces a design environment FRIDGE, which supports transformation of signal processing algorithms coded in floating-point to a fixed-point representation.  ...  The first paper proposes a lightweight floating point arithmetic, a family of customizable floating-point data formats, which bridges the design gap between software and hardware.  ... 
doi:10.1155/s1110865702001841 fatcat:lhhw4t7s5fan3ivs3ui5ch677u

Learning-based non-rigid image registration using prior joint intensity distributions with graph-cuts

Ronald W. K. So, Albert C. S. Chung
2011 2011 18th IEEE International Conference on Image Processing  
In this paper, we propose a new formulation for the novel KLD based similarity measure such that it can be exploited in Markov random field (MRF) based non-rigid registration framework with the graph-cuts  ...  The displacements of other pixels are estimated by the interpolation among its neighborhood control points by a B-splines function.  ...  GC-D 12 can significantly reduce the averaged registration errors among different tissues as compared with GC-MI and GC-SAD (see the last row in Table 1 ).  ... 
doi:10.1109/icip.2011.6116652 dblp:conf/icip/SoC11 fatcat:qltgxyzlkjeefo2uphiteejvsy

Geometric Tiling for Reducing Power Consumption in Structured Matrix Operations

G. Chen, L. Xue, J. Kim, K. Sobti, L. Deng, X. Sun, N. Pitsianis, C. Chakrabarti, M. Kandemir, N. Vijaykrishnan
2006 2006 IEEE International SOC Conference  
This work focuses on reducing power consumption while maintaining the efficiency and accuracy of matrix computations using both algorithmic and architectural means.  ...  The integer index in each graph indicates an evaluation order. (a) a point distribution in a two-dimensional sub-domain.  ...  EXPERIMENTAL EVALUATION The important point to note is that one may not need the full 32 bits for all the floating-point operations performed during geometric tiling.  ... 
doi:10.1109/socc.2006.283861 dblp:conf/socc/ChenXKSDSPCKV06 fatcat:bhxvspngnfb5lockmhcdqtyqtm

Assessing Impact of Data Partitioning for Approximate Memory in C/C++ Code [article]

Soramichi Akiyama
2020 arXiv   pre-print
Among them, two have a pointer and a non-pointer member together (criterion 2) and three have a floating point number and other members together (criterion 3).  ...  Approximate memory is a technique to mitigate the performance gap between memory subsystems and CPUs with its reduced access latency at a cost of data integrity.  ...  [C3]: If the target data type includes a floating point number, it is possible that the floating point number is approximate data.  ... 
arXiv:2004.01637v1 fatcat:yqfss4xrurd7vhfocly26oxubq
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