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Power Efficient Design of DisplayPort (7.0) Using Low-voltage differential signaling IO Standard Via UltraScale Field Programming Gate Arrays
2017
Gyancity Journal of Electronics and Computer Science
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The proposed design of vhdl based design of DisplayPort (7.0) using LVDS IO Standard offers no power consumption for DisplayPort (7.0) in standby mode. ...
The vhdl based design of DisplayPort (7.0) using LVDS IO Standard will be helpful to process the high resolution video at low power consumption. ...
It has been demonstrated in [8] [9] that for different variation in suitable IO Standard the power consumption of device can be reduced depend upon the core voltage of Field Programming Gate Array (FPGA ...
doi:10.21058/gjecs.2017.21004
fatcat:fe3qsranbbfihp2233knmobywm
Hardware implementation of a FPGA-based universal link for LVDS communications
2015
2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS)
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We present the first hardware implementation for a FPGA-based universal link for the transmission of different low-voltage differential signaling (LVDS) connections through a single LVDS connection between ...
The main objective of this work is to reduce the number of wires in a network, for example in some satellites, with several groups of devices, to a single LVDS connection. ...
Fig. 1 . 1 Universal link for N different communications channels (c 0 , c 1 , · · · , c N −1 ) using LVDS. (a) N communication systems working individually. (b) Same system using an universal link. ...
doi:10.1109/lascas.2015.7250480
dblp:conf/lascas/SanchezPML15
fatcat:g55y4i2edra5xnabclbuq7t6gi
Live demonstration: A scalable 32-channel neural recording and real-time FPGA based spike sorting system
2015
2015 IEEE Biomedical Circuits and Systems Conference (BioCAS)
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The hardware consists of: an Intan RHD2132 neural amplifier; a low power Igloo ® nano FPGA; and an FX3 USB 3.0 controller. ...
Graphical User Interfaces for controlling the system, displaying real-time data, and template generation with a modified form of WaveClus are demonstrated. ...
ACKNOWLEDGEMENT This research has been funded by the Engineering and Physical Sciences Research Council (EPSRC) grant refs: EP/I000569/1 and EP/K015060/1. ...
doi:10.1109/biocas.2015.7348330
dblp:conf/biocas/WilliamsLJC15
fatcat:2qesllam6rf2jesq3s2nnxomci
Backplane Serial Signaling And Protocol For Telecom Systems
2010
Zenodo
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For combination high reliability and low cost protocol property, we applied high level data link control (HDLC) protocol with low voltage differential signaling (LVDS) bus for card to card communicated ...
In this paper, we implement a modern serial backplane platform for telecommunication inter-rack systems. ...
ACKNOWLEDGMENT The authors would like to thank Iran Telecom Research Center (ITRC) organization for full project supporting. ...
doi:10.5281/zenodo.1072329
fatcat:qzaix2lp65gf5hgv632g53qmhy
Flexible FPGA-based controller architecture for five-fingered dexterous robot hand with effective impedance control
2009
2009 IEEE International Conference on Robotics and Biomimetics (ROBIO)
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The key feature of the hardware system is a dual-processor architecture based controller, one of which is used for data communication control and the other for joint and object level control. ...
A Multiprocessor structure based on field programming gate array (FPGA) is proposed to realize the high-level hand impedance controller. ...
Benedikt Pleintinger of the German Aerospace Center (DLR) for their technical support. ...
doi:10.1109/robio.2009.5420731
dblp:conf/robio/ChenLWLXJLFL09
fatcat:er5qvabobzb3dnfsfu4we4wesu
Design and implementation of a low-cost fault-tolerant on-board computer for micro-satellite
2012
7th International Conference on Communications and Networking in China
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The purpose of this paper is to present a solution for developing a low-cost, low power consumption and reliable OBC system for micro-satellites. ...
However, the resources on micro-satellites are so limited that the OBC should not only meet the requirements of excellent performance and high reliability, but also be in proper power consumption and cost ...
The OBC also uses serial interfaces and low-voltage differential signaling (LVDS) links to communicate with other subsystems onboard the satellite in addition to CAN interfaces. ...
doi:10.1109/chinacom.2012.6417462
dblp:conf/chinacom/TianYYL12
fatcat:2qadesy3wnfi5ih4b4n7clfrke
Portable data acquisition system based on FPGA and USB
2013
International Journal of Intelligent Engineering and Systems
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In this paper, we designed a high-speed, high-precision, portable data acquisition and processing system in Altera Corporation cyclone II FPGA platform, and achieved the communication between the system ...
We used AD9467 as the core chip of the A/D module, and the characteristics and specific circuit design of AD9467 are explained in detail; the FPGA module is the core of the entire system, which is not ...
Acknowledgments This work is supported by the National Science Foundation of China (grants 61071204) and the Development Foundation of Tianjin University of Technology and Education (grants KJY11-3). ...
doi:10.22266/ijies2013.0630.03
fatcat:ec4342kryvcmroz7ul2eqqi5kq
Design and implementation of electrowetting multi-gray dynamic display driving system
电润湿电子纸多灰度动态显示驱动系统设计与实现
2018
Chinese Journal of Liquid Crystals and Displays
电润湿电子纸多灰度动态显示驱动系统设计与实现
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光电工程, 2019, 46(6): 180623 Abstract: In order to achieve electrowetting real-time display, a display driving system, consisting of a DVI video codec system and FPGA timing control system, is designed. ...
FPGA is responsible for buffering and processing of video data and for controlling electrowetting driving waveforms. This paper also proposes an improved multi-grayscales dy- ...
Design of
High-Speed
LVDS
data
communication
link
using
FPGA[C]//International Conference on Information and Com-
munication Technology for Intelligent Systems. Cham, 2017:
1-9. ...
doi:10.3788/yjyxs20183303.0213
fatcat:c3zd2vmifbeenci2qijjpfkua4
MDDI Protocol Packet Generation Method of Mobile System
2014
International Journal of Multimedia and Ubiquitous Engineering
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In this paper, the method of creating data in software, which was notpresent in the previous FPGA is proposed for design of data transmitter using the MDDI interface method. ...
In this study, it is proposed to use software to create MDDI protocol packet which is required for the display device. ...
This packet is useful for saving power after the link is shut down and the static image is transmitted to the mobile communication device of client. ...
doi:10.14257/ijmue.2014.9.1.14
fatcat:tn35dballndhzl4ifoljx5pra4
A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications
2016
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. ...
This approach allows to alter the design, according to the system requirements, with simple modifications in the firmware. ...
The authors would like to gratefully acknowledge Bishnu Patra for the design and layout of the PCB and Fabio Sebastiano for his support and fruitful discussions. ...
doi:10.1109/tcsi.2016.2599927
fatcat:u2qv4geko5hl5dqq5ebjxrxg2u
Development of the scalable readout system for micro-pattern gas detectors and other applications
2013
Journal of Instrumentation
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The board is based around a Virtex 5 Xilinx FPGA, integrating a 2 Gbit DDR2 memory chip, one SFP connector for Gigabit Ethernet communication, general purpose NIM and LVDS interfaces and two LVDS DTCC ...
The link uses LVDS signaling over shielded CAT6/7 cables, taking advantage of the high IO density and speed of modern FPGAs. ...
doi:10.1088/1748-0221/8/03/c03015
fatcat:bze536y6h5furcw74jpmazkygm
KM3NeT front-end and readout electronics system: hardware, firmware and software
[article]
2019
arXiv
pre-print
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By design, the total electrical power consumption of an optical module has been capped at seven watts. ...
This paper presents an overview of the front-end and readout electronics system inside the optical module, which has been designed for a 1~ns synchronization between the clocks of all optical modules in ...
Acknowledgments The authors acknowledge the financial support of the funding agencies: Agence Nationale de la Recherche (contract ANR-15-CE31-0020), Centre National de la Recherche Scientifique (CNRS), ...
arXiv:1907.06453v2
fatcat:svjwisg3ibdobdouiczxwb6yz4
A data formatter for the ATLAS Fast Tracker
2012
2012 18th IEEE-NPSS Real Time Conference
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Abstract-The Fast TracKer (FTK) is an upgrade to the ATLAS level-2 trigger. ...
We present an overview of the Data Formatter system, which is designed to remap, share and reformat the Pixel and SCT module data to match the geometry of the FTK trigger towers. ...
Power consumption on the Data Formatter board is estimated to be less than 30W (not including the mezzanine cards). ...
doi:10.1109/rtc.2012.6418210
fatcat:cw752lgg5fgrpfo4lckdjtkhsy
High-Speed Data Processing Module for LLRF
2015
IEEE Transactions on Nuclear Science
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The module provides the processing power, data memory, communication links, reference clock, trigger and interlock signals that are required in modern LLRF control systems. ...
This paper discusses the requirements for the digital real-time data processing module, presents the laboratory performance evaluation and verification in Cryo-Module Test Bench (CMTB) at DESY. ...
The DAMC-TCK7 has a sufficient thermal and power consumption margin even for complex algorithms, consuming many FPGA resources and GTX links. ...
doi:10.1109/tns.2015.2416120
fatcat:jghmpcjl4rb6fmaz7otkj6czqq
High-speed data processing module for LLRF
2014
2014 19th IEEE-NPSS Real Time Conference
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The module provides the processing power, data memory, communication links, reference clock, trigger and interlock signals that are required in modern LLRF control systems. ...
This paper discusses the requirements for the digital real-time data processing module, presents the laboratory performance evaluation and verification in Cryo-Module Test Bench (CMTB) at DESY. ...
The DAMC-TCK7 has a sufficient thermal and power consumption margin even for complex algorithms, consuming many FPGA resources and GTX links. ...
doi:10.1109/rtc.2014.7097409
fatcat:ms46xkf6l5er7guvfd5rcxt3h4
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