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Reconfiguring the Imaging Pipeline for Computer Vision [article]

Mark Buckler, Suren Jayasuriya, Adrian Sampson
2017 arXiv   pre-print
We examine the role of the image signal processing (ISP) pipeline in computer vision to identify opportunities to reduce computation and save energy.  ...  We use eight computer vision algorithms and a reversible pipeline simulation tool to study the imaging system's impact on vision performance.  ...  Discussion We advocate for adding a vision mode to the imaging pipelines in mobile devices.  ... 
arXiv:1705.04352v3 fatcat:ffcipyjsvjgwlo4rv3oumyonqe

A Parallel Reconfigurable Architecture for Real-Time Stereo Vision

Lei Chen, Yunde Jia
2009 2009 International Conference on Embedded Software and Systems  
In this paper, a parallel reconfigurable architecture is proposed for real-time stereo vision computation.  ...  Based on the proposed architecture and design method, we have developed a miniature stereo vision machine (MSVM33) to generate high-resolution dense disparity maps at the video rate for real-time applications  ...  Acknowledgements This work was partially supported by the Natural Science Foundation of China (60675021), the Chinese High-Tech Program (2006AA01Z120), and Beijing key discipline program.  ... 
doi:10.1109/icess.2009.18 dblp:conf/icess/ChenJ09 fatcat:3iyderhilvgtbphf5ogs3a26pe

VoC: a reconfigurable matrix for stereo vision processing

R.P. Jacobi, R.B. Cardoso, G.A. Borges
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
This paper presents a reconfigurable matrix VoC that can be applied to stereo vision computation.  ...  The pipelined version mapped to Xilinx FPGA could be simulated at 158 MHz, producing 1,42 billion matchings per second.  ...  Conclusions A parallel reconfigurable architecture for stereo video vision is proposed in the work. It implements the SAD computation either for blocks of 7x7 pixels or for blocks of 5x5 pixels.  ... 
doi:10.1109/ipdps.2006.1639454 dblp:conf/ipps/JacobiCB06 fatcat:an4ofg2wf5amvpt2nmkgfcucxq

Adaptive Resolution-Based Tradeoffs for Energy-Efficient Visual Computing Systems

Robert LiKamWa, Jinhan Hu, Venkatesh Kodukula, Yifei Liu
2021 IEEE pervasive computing  
MULTIRESOLUTION OPPORTUNITIES IN THE VISUAL COMPUTING PIPELINE The visual computing pipeline uses: 1) image sensors to capture pixels, 2) image signal processors to perform color conversion and place the  ...  Other Approaches to Efficient Visual Computing. Reconfigurable image sensing pipelines would pair well with several recent efforts to reduce the energy footprint of visual computing.  ...  in image sensors in the multiresolution computing pipeline.  ... 
doi:10.1109/mprv.2021.3052528 fatcat:4m5bzc4a4bcwng6xeuaotdxmca

Reconfigurable Processor for Binary Image Processing

Bin Zhang, Kuizhi Mei, Nanning Zheng
2013 IEEE transactions on circuits and systems for video technology (Print)  
The reconfigurable binary processing module, which consists of mixed-grained reconfigurable binary compute units and output control logic, performs binary image processing operations, especially mathematical  ...  Binary image processing is a powerful tool in many image and video applications. A reconfigurable processor is presented for binary image processing in this paper.  ...  Most reconfigurable vision chips realize reconfigurable computing by processing an element array [10] , [11] .  ... 
doi:10.1109/tcsvt.2012.2223872 fatcat:szrryqj6nfhkbc2gzpqvxese2q

A Dynamically Reconfigurable Architecture Combining Pixel-Level SIMD and Operation-Pipeline Modes for High Frame Rate Visual Processing

Nao Iwata, Shingo Kagami, Koichi Hashimoto
2007 2007 International Conference on Field-Programmable Technology  
This paper describes a new reconfigurable processor architecture specialized for high frame rate visual processing.  ...  This architecture employs a 2-D mesh processing element (PE) array in which the PEs can be configured to operate as SIMD arrays or operation-pipeline trees depending on image processing algorithms so that  ...  In these graylevel processing, the bits expressing the graylevel of input image must be allocated for each pixel at least, and in general much more is needed as temporary storage for computation.  ... 
doi:10.1109/fpt.2007.4439276 dblp:conf/fpt/IwataKH07 fatcat:6rt5elg4zbfu3omg6vn5knpf4y


Kishan Shivhare, Gaurav Bhardwaj
2016 International Journal of Advanced Research  
Architecture:- The processor we are currently using for binary image processing has been designed for applications in image or video processing, computer vision, machine intelligence, identification and  ...  , document authentication, and computer vision.  ... 
doi:10.21474/ijar01/787 fatcat:sdngspuzuzd5tftpov52y332ja

Page 142 of Journal of Research and Practice in Information Technology Vol. 24, Issue 4 [page]

1992 Journal of Research and Practice in Information Technology  
ARCHITECTURES FOR COMPUTER V1S!QN = (a) Reconfigurable system such as TRAC. Figure 2.  ...  . 142 THE AUSTRALIAN COMPUTER JOURNAL, VOL. 24, No. 3, NOVEMBER 1992 (b) Reconfigurable system such as PASM. based vision operations.  ... 

Reconfigurable computing for future vision-capable devices

Miguel Bordallo Lopez, Alejandro Nieto, Olli Silven, Jani Boutellier, David Lopez Vilarino
2015 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)  
Mobile devices have been identified as promising platforms for interactive vision-based applications.  ...  In this context, the integration of reconfigurable architectures on mobile devices allows dynamic reconfiguration to match the computation and data flow of interactive applications, demonstrating significant  ...  Experimental setup For experimental purposes, to provide a comparison with the selected reconfigurable architectures, we benchmark different computer vision kernels across several current platforms.  ... 
doi:10.1109/samos.2015.7363657 dblp:conf/samos/LopezNSBV15 fatcat:ljzx4e4iv5a6jidj2abdwcefo4

Reconfigurable Morphological Processor for Grayscale Image Processing

Bin Zhang
2021 Electronics  
The RGPM, which consists of four grayscale computing units, conducts grayscale morphological operations and implements related algorithms of more than 100 f/s for a 1024 × 1024 image.  ...  The periphery circuits control the entire image processing and dynamic reconfiguration process.  ...  Architecture The grayscale image processor is designed for various applications in computer vision, image analysis, medical image processing, and video segmentation systems.  ... 
doi:10.3390/electronics10192429 fatcat:47zjlve4pndzvoe26reib72oi4

Highly Scalable Monitoring System on Chip for Multi-Stream Auto-Adaptable Vision System

A. Isavudeen, N. Ngan, E. Dokladalova, M. Akil
2017 Proceedings of the International Conference on Research in Adaptive and Convergent Systems - RACS '17  
This makes the design of computing resources very arduous task in the context of latency critical application. The proposed solution is based on the self-awareness of such vision system.  ...  The integration of multiple and technologically heterogeneous sensors (infrared, color, etc) in vision systems tends to democratize.  ...  For instance, the vision system shifts to the infrared sensor for night vision when it Fig. 12 : Use-case 2 : stream type modification is getting night.  ... 
doi:10.1145/3129676.3129721 dblp:conf/racs/IsavudeenNDA17 fatcat:243trsyjv5alhalurxzp3jd7si

2.2 A 978GOPS/W Flexible Streaming Processor for Real-Time Image Processing Applications in 22nm FDSOI

Sander Smets, Toon Goedeme, Anurag Mittal, Marian Verhelst
2019 2019 IEEE International Solid- State Circuits Conference - (ISSCC)  
Providing a deep reconfigurable pipeline, this design facilitates the mapping and execution of complex vision tasks, like dense optic flow in real-time (30fps VGA) at low power (10.7mW), marking a 5.8×  ...  Note that reconfiguring the architecture and clearing the pipeline only blocks execution around 3% of the time and only accounts for 2% of the overall energy consumption.  ...  Acknowledgements: The authors would like to thank Research Foundation Flanders (FWO) for supporting the work of S. Smets by a Doctoral Fellowship, and GlobalFoundries for chip fabrication support.  ... 
doi:10.1109/isscc.2019.8662346 dblp:conf/isscc/SmetsGMV19 fatcat:d45qjpw6wrbi7gzr6t2x2mtztu

Time-Shared Execution of Realtime Computer Vision Pipelines by Dynamic Partial Reconfiguration [article]

Marie Nguyen, James C. Hoe
2018 arXiv   pre-print
This paper presents an FPGA runtime framework that demonstrates the feasibility of using dynamic partial reconfiguration (DPR) for time-sharing an FPGA by multiple realtime computer vision pipelines.  ...  The paper also reports the performance of realtime computer vision pipelines when time-shared.  ...  We demonstrated through a working runtime framework the practical feasibility of timing-sharing by vision pipelines at useful frame rates-30 fps for 1080p and 60 fps for 720p on the Xilinx ZC706 board.  ... 
arXiv:1805.10431v3 fatcat:4elde46cr5h2tk3moehivukiiy

A Compact 3D Camera Suited for Mobile and Embedded Vision Applications

Stefano Mattoccia, Ilario Marchio, Marco Casadio
2014 2014 IEEE Conference on Computer Vision and Pattern Recognition Workshops  
This paper describes a compact 3D camera based on passive stereo vision technology suited for mobile/embedded vision applications.  ...  to state-of-the-art stereo vision algorithms.  ...  CONCLUSIONS In this paper we have outlined an optimized computing architecture, based on a low cost FPGA, and the processing pipeline for a stereo camera suited for embedded/mobile vision applications.  ... 
doi:10.1109/cvprw.2014.36 dblp:conf/cvpr/MattocciaMC14 fatcat:udl2uhqfovcrppvmrqi2574avm

Median and Morphological Specialized Processors for a Real-Time Image Data Processing

Kazimierz Wiatr
2002 EURASIP Journal on Advances in Signal Processing  
This paper presents the considerations on selecting a multiprocessor MISD architecture for fast implementation of the vision image processing.  ...  Using the author's earlier experience with real-time systems, implementing of specialized hardware processors based on the programmable FPGA systems has been proposed in the pipeline architecture.  ...  ACKNOWLEDGEMENT This work was supported by the Polish Science Committee.  ... 
doi:10.1155/s1110865702000422 fatcat:gtiqshdk2rdxzksbqbbyzz56qy
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