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A Survey of Aging Monitors and Reconfiguration Techniques [article]

Leonardo Rezende Juracy, Matheus Trevisan Moreira, Alexandre de Morais Amory, Fernando Gehm Moraes
2020 arXiv   pre-print
Results show that the most common monitor type used for aging detection is to monitor timing errors, and the most common reconfiguration technique used to deal with aging is voltage scaling.  ...  Furthermore, most of the literature contributions are in the digital field, using hardware solutions for monitoring aging in circuits.  ...  Most software applications act on reconfiguring the circuit after aging detection.  ... 
arXiv:2007.07829v1 fatcat:2syuq4acm5ci3kafbxljvzbguq

Online Fault Detection, Diagnosis and Repair using RA

2015 International Journal of Science and Research (IJSR)  
Reconfigurable test architecture works alongside the controllers for online concurrent fault detection.  ...  But for this circuit have to switch in off-line mode which unnecessary waste time and power to avoid this best method is online bist In this paper BIST architecture is implemented for Detection, Diagnosis  ...  In this a coding based method of parity checking is used especially for detecting memory and data transmission errors [6] .  ... 
doi:10.21275/v4i11.nov151049 fatcat:doe2mlvn5baw7iyvktvugc5qme

Fault tolerant methods for reliability in FPGAs

Edward Stott, Pete Sedcole, Peter Y. K. Cheung
2008 2008 International Conference on Field Programmable Logic and Applications  
Fortunately FPGAs have the ability to reconfigure in the field and at runtime, thus providing opportunities to overcome some of these issues.  ...  This paper provides the first comprehensive survey of fault detection methods and fault tolerance schemes specifically for FPGAs, with the goal of laying a strong foundation for future research in this  ...  Redundant/concurrent error detection uses additional logic as a means of detecting when a logic function is not generating the correct output. 2.  ... 
doi:10.1109/fpl.2008.4629973 dblp:conf/fpl/StottSC08 fatcat:gxrojxqwqjco7f7eejzyj2p4uq

PVT-induced timing error detection through replica circuits and time redundancy in reconfigurable devices

Dawood Alnajjar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
2013 IEICE Electronics Express  
When attaining a false negative error of zero, the probability of error detection and reexecution in time-shifted redundant circuits is comparable to, or rather smaller than that of the path-replica circuits  ...  For an approximately similar false positive error probability for the path-replica and circuit-replica, the false negative error probability of the circuit-replica is approximately two orders of magnitude  ...  Acknowledgment The VLSI chip in this study has been fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with eShuttle Inc. and  ... 
doi:10.1587/elex.10.20130081 fatcat:iongwk5h7ncctfj6dbnh5iktgi

Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices

Dawood Alnajjar, Masanori Hashimoto, Takao Onoye, Yukio Mitsuyama
2012 2012 International Conference on Reconfigurable Computing and FPGAs  
When attaining a false negative error of zero, time-shifted redundant circuits achieves one order of magnitude less in false positive error probability than that of the replica circuits.  ...  For an approximately similar false positive error probability for time-shifted redundant circuits and replica circuits, the false negative error probability of time-shifted redundant circuits is approximately  ...  of using time-shifted redundant circuits and replica circuits in detecting and predicting timing error occurrences in a real circuit mapped on a reconfigurable device.  ... 
doi:10.1109/reconfig.2012.6416787 dblp:conf/reconfig/AlnajiarHOM12 fatcat:fecbxmkzg5c5hpsdcvn2whg7uy

Designing fault tolerant systems into SRAM-based FPGAs

Fernanda Lima, Luigi Carro, Ricardo Reis
2003 Proceedings of the 40th conference on Design automation - DAC '03  
The new technique proposed in this paper was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power  ...  However, TMR comes with high area and power dissipation penalties.  ...  Figure 3 presents the DWC approach able to perform concurrent error detection (CED), called hot backup DWC-CED.  ... 
doi:10.1145/775832.775997 dblp:conf/dac/LimaCR03 fatcat:lcpudybsxve4hotdgbs3pov6ce

Designing fault tolerant systems into SRAM-based FPGAs

Fernanda Lima, Luigi Carro, Ricardo Reis
2003 Proceedings of the 40th conference on Design automation - DAC '03  
The new technique proposed in this paper was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power  ...  However, TMR comes with high area and power dissipation penalties.  ...  Figure 3 presents the DWC approach able to perform concurrent error detection (CED), called hot backup DWC-CED.  ... 
doi:10.1145/775995.775997 fatcat:vtuahcag5vgq7hcgx4a4htz4yy

Microprocessor fault-tolerance via on-the-fly partial reconfiguration

Stefano Di Carlo, Andrea Miele, Paolo Prinetto, Antonio Trapanese
2010 2010 15th IEEE European Test Symposium  
software the tasks that were executed in hardware before a fault and the subsequent reconfiguration happened.  ...  The advantage of the proposed approach is that thanks to a hardware hypervisor, the CPU is totally unaware of the reconfiguration happening in real-time, and there's no dependency on the CPU to perform  ...  Online concurrent error detection can be accomplished by using error detection codes, such as parity, on the ALU inputs, and an efficient concurrent code prediction logic, as proposed in [9] .  ... 
doi:10.1109/etsym.2010.5512759 dblp:conf/ets/CarloMPT10 fatcat:tgscbcrponenfjpypk5kp2sl6u

An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures

S. Baloch, T. Arslan, A. Stoica
2006 2006 International Conference on Field Programmable Logic and Applications  
As the microelectronics industry has advanced, Integrated Circuit (IC) design and reconfigurable architectures (FPGAs, reconfigurable SoC and etc) have experienced dramatic increase in density and speed  ...  Due to transient nature of single event upsets (SEUs), these are most difficult to avoid in space-borne reconfigurable architectures.  ...  Programmable Logic Devices (PLD), and more specifically Field Programmable Gate Arrays (FPGA), are replacing traditional logic circuits by offering the advantages of high integration (small size, low power  ... 
doi:10.1109/fpl.2006.311295 dblp:conf/fpl/BalochAS06 fatcat:xy2fdkwbcrfmpmrd5o3cq4gtw4

On-Orbit Flight Results from the Reconfigurable Cibola Flight Experiment Satellite (CFESat)

Michael Caffrey, Keith Morgan, Diane Roussel-Dupre, Scott Robinson, Anthony Nelson, Anthony Salazar, Michael Wirthlin, William Howes, Daniel Richins
2009 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines  
In addition, this paper will describe the results from several SEU detection circuits that were performed on the spacecraft.  ...  The CFE satellite was launched on March 8, 2007 in low-earth orbit and has operated extremely well since its deployment.  ...  SEU1 -Configuration Upsets The first SEU detection experiment, named SEU1, was designed as a low-power simple circuit that does not perform in-circuit detection.  ... 
doi:10.1109/fccm.2009.22 dblp:conf/fccm/CaffreyMRRNSWHR09 fatcat:ysox2kcot5ezteltl5c3ehhxoa

Design and Testing of 16 bit Carry Save Adder using Reconfigurable LFSR

2020 International Journal of Advanced Trends in Computer Science and Engineering  
High speed and low power are the main parameters that are targeted by modern circuit designers.  ...  The ever increasing applications of integrated circuits in the day-to-day useful electronic gadgets are the driving force for the development of low power designs of configurable hardware designs.  ...  This paper discusses read defects with classic errors and increases design efficiency and testing time for detecting defects. The implementation of low power BIST is taken into account critically.  ... 
doi:10.30534/ijatcse/2020/156952020 fatcat:fg4znbugd5gbpb2izyvea2ejta

ASM-ROBOT: A Cyber-Physical Home Automation Controller with Memristive Reconfigurable State Machine

Kennedy Chinedu Okafor, Omowunmi Mary Longe
2022 International Journal of Advanced Computer Science and Applications  
A process control architecture that supports Concurrent Wireless Data Streams and Power-Transfer (CWDSPT) is developed.  ...  Received signals are error-buffered while gathering control variables' status. Transceiver Memristive neuromorphic circuits are introduced for computational acceleration in the design.  ...  In cases of Mixed-signal analog/digital neuromorphic circuits, there has been the characterization of such circuits using ultra-low power consumption, real-time processing abilities, and low-latency response  ... 
doi:10.14569/ijacsa.2022.01301103 fatcat:v3itcwva3bap7hmgjxwvsgqim4

A reconfigurable parallel signature analyzer for concurrent error correction in DRAM

P. Mazumder, J.H. Patel, J.A. Abraham
1990 IEEE Journal of Solid-State Circuits  
An efficient strategy to utilize a parallel signature analyzer (PSA) for concurrent soft-error correction in DRAM'S is described.  ...  Such an error-correction circuit (ECC) significantly improves the reliability of the memory system.  ...  Thus the proposed technique of concurrent error detection and correction uses a two-level parity coding.  ... 
doi:10.1109/4.102687 fatcat:pc2ki7ple5asrfhjzuskw7e44a

Improving Fault Tolerance of Network-on-Chip Links via Minimal Redundancy and Reconfiguration

Hamed S. Kia, Cristinel Ababei
2011 2011 International Conference on Reconfigurable Computing and FPGAs  
Because different segments of the spare wires address different errors from different segments, the proposed reconfigurable link structure can tolerate a larger number of errors with a reduced number of  ...  We propose to partition links in a network-on-chip into multiple segments and use spare wires at the level of each segment to address permanent errors due to manufacturing or wearout defects.  ...  Once a fault is detected by the error detection logic, the link is reconfigured to replace the faulty wire with one of the healthy k redundant wires.  ... 
doi:10.1109/reconfig.2011.52 dblp:conf/reconfig/KiaA11 fatcat:tfzmhcybuzf4xkaspapvhm4o2y

Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

I. Herrera-Alzu, M. Lopez-Vallejo
2013 IEEE Transactions on Nuclear Science  
SRAM-based FPGAs are in-field reconfigurable an unlimited number of times.  ...  In order to be effective they need to be complemented with configuration memory scrubbing, which allows error mitigation and prevents failures due to error accumulation.  ...  Virtex-5 also provides a built-in readback CRC circuit for overall memory error detection.  ... 
doi:10.1109/tns.2012.2231881 fatcat:y34el2up7nhvzbrhecksrkogri
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