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Reconfigurable hardware implementation of a modified chaotic filter bank scheme

A. Pande, J. Zambreno
2010 International Journal of Embedded Systems  
In this paper, we first present an improved scheme to alleviate the weaknesses of the chaotic filter bank scheme, and add enhanced security features, to form a modified chaotic filter bank (MCFB) scheme  ...  Next, we present a reconfigurable hardware implementation of the MCFB scheme.  ...  of the authors, this is the first hardware implementation of a chaotic filter bank scheme in hardware. 3 A clock frequency of 88 MHz was obtained for a Virtex-5 XC5VLX330 FPGA.  ... 
doi:10.1504/ijes.2010.039028 fatcat:xoc5f6ai3zbblp3xh3lov5dzee

Multiple perspectives on the hardware implementations of biological neuron models and programmable design aspects

Nimet KORKMAZ, İsmail ÖZTÜRK, Recai KILIÇ
2016 Turkish Journal of Electrical Engineering and Computer Sciences  
The aim of this paper is to present a comparative study about programmable and reconfigurable implementations of the FitzHugh-Nagumo, Izhikevich, and Hindmarsh-Rose neuron models.  ...  modification, and software control for programmable and reconfigurable implementations of neuron models and neural structures, they are preferred in these implementations as analog and digital programmable  ...  bank.  ... 
doi:10.3906/elk-1309-5 fatcat:smn2hv3hojaqlnjuugpwbf2mp4

2020 Index IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 67

2020 IEEE Transactions on Circuits and Systems - II - Express Briefs  
1074-1078 Iu, H.H.C., see Eshraghian, J.K., TCSII May 2020 956-960 Iu, H.H.C., see Yu, D., 1334-1338 Iu, H.H.C., see Wang, L., TCSII Oct. 2020 2084-2088 J Jabavathi, J.D., and Sait, H., Design of  ...  Novel Approximation Methodology and Its Efficient VLSI Implementation for the Sigmoid Function; 3422-3426 Qiu, Y., see Qin, Z., TCSII Dec. 2020 3422-3426 Qu, L., see Zhao, Z., TCSII May 2020 931-935  ...  Ismail, A., +, TCSII March 2020 600-604 Efficient Implementation of a Threshold Modified Min-Sum Algorithm for LDPC Decoders.  ... 
doi:10.1109/tcsii.2020.3047305 fatcat:ifjzekeyczfrbp5b7wrzandm7e

Field Programmable Gate Array Applications—A Scientometric Review

Juan Ruiz-Rosero, Gustavo Ramirez-Gonzalez, Rahul Khanna
2019 Computation  
Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems  ...  Also, we present an evolution and trend analysis of the related applications.  ...  Hardware Implementation of Parallel FIR Filter Using Modified Distributed Arithmetic.  ... 
doi:10.3390/computation7040063 fatcat:wxtatzsvvnfopghdfl25hcfc2a

The M2DC Project: Modular Microserver DataCentre

Mariano Cecowski, Giovanni Agosta, Ariel Oleksiak, Michal Kierzynka, Micha vor dem Berge, Wolfgang Christmann, Stefan Krupop, Mario Porrmann, Jens Hagemeyer, Rene Griessl, Meysam Peykanu, Lennart Tigges (+13 others)
2016 2016 Euromicro Conference on Digital System Design (DSD)  
The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware.  ...  This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs.  ...  Highlighting the use of reconfigurable hardware as a platform for digital controller, the only implementations shown in [4] are from the field of control engineering.  ... 
doi:10.1109/dsd.2016.76 dblp:conf/dsd/CecowskiAOKBCKP16 fatcat:bu4nbkqaejebjafrotibui6mkq

Neuromorphic Photonics, Principles of [chapter]

Bhavin J. Shastri, Alexander N. Tait, Thomas Ferreira de Lima, Mitchell A. Nahmias, Hsuan-Tung Peng, Paul R. Prucnal
2018 Encyclopedia of Complexity and Systems Science  
absence of a robust photonic integration industry.  ...  We conclude with a future outlook of neuro-inspired photonic processing.  ...  A reconfigurable filter can be implemented by a MRR-in simple words, a waveguide bent back on itself to create an interference condition.  ... 
doi:10.1007/978-3-642-27737-5_702-1 fatcat:h3qtsskafzgq3ipmtxa2xlfksi

Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing

Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai
2018 Complexity  
A protocomputational architecture is presented that implements the ancient reaction-diffusion model as a microelectronic hardware.  ...  Real-time video processing results at 30 fps are achieved using an FPGA physical implementation of the proposed protoarchitecture.  ...  Acknowledgments This study was supported by the JSPS Grants-in-Aid for JSPS Fellows and a Grant-in-Aid for Scientific Research on Innovative Areas [2511001503] from the Ministry of Education, Culture,  ... 
doi:10.1155/2018/3618621 fatcat:phbvjrtrvffihnbsobkvvwgvai

Neuromorphic microelectronics from devices to hardware systems and applications

Alexandre Schmid
2016 Nonlinear Theory and Its Applications IEICE  
A regain of interest has been observed in the middle of the 2010s', which manifests itself from the emergence of large-scale projects integrating various computational and hardware perspectives, by the  ...  This paper reviews research directions and methods of neuromorphic microelectronics hardware, the developed hardware and its performance, and discusses current issues and potential future developments.  ...  A certain level of programmability should be offered by software reconfigurability of the hardware.  ... 
doi:10.1587/nolta.7.468 fatcat:2lvkjxhetnghtmbbow4mfcqqjm

2021 Index IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 68

2021 IEEE Transactions on Circuits and Systems - II - Express Briefs  
The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination.  ...  ., +, TCSII Jan. 2021 161-165 Design and Implementation of Low Complexity Reconfigurable Filtered-OFDM-Based LDACS.  ...  Souza, C.E.C., +, TCSII April 2021 1472-1476 Design and Implementation of Low Complexity Reconfigurable Filtered-OFDM-Based LDACS.  ... 
doi:10.1109/tcsii.2022.3144928 fatcat:bm53w7gva5bthholfhhiq4yg3a

IJATES^2 Vol. 2, No.2

Jaroslav Koton
2013 International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems  
FIR filter can be implemented in a conventional scheme using delay elements.  ...  Reconfigurable Hardware The reconfigurable devices, firstly introduced by G.  ...  For simplicity of analysis we use the orthogonality principle, instead of the MMSE solution [15] .  ... 
doi:10.11601/ijates.v2i2.56 doaj:b7f35f4f85f741ad9fee49ef554506c7 fatcat:46hsbtdsafc25hc3eihlvos42u

A Survey on Compressive Spectrum Sensing for Cognitive Radio Networks

Salma Benazzouza, Mohammed Ridouani, Fatima Salahdine, Aawatif Hayar
2019 2019 IEEE International Smart Cities Conference (ISC2)  
It also provides examples of innovative applications of compressive spectrum sensing including IoT, smart city and 5th generation of mobile networks.  ...  better and faster results using the sparse structure of the radio spectrum.  ...  detection [8] ,filter bank detection [9] , and blind spectrum sensing [10] .  ... 
doi:10.1109/isc246665.2019.9071710 dblp:conf/isc2/BenazzouzaRSH19 fatcat:e6oemvwmwzem7kkq7dni62hz6u

A Survey on Silicon Photonics for Deep Learning [article]

Febin P Sunny, Ebadollah Taheri, Mahdi Nikdast, Sudeep Pasricha
2021 arXiv   pre-print
This article surveys the landscape of silicon photonics to accelerate deep learning, with a coverage of developments across design abstractions in a bottom-up manner, to convey both the capabilities and  ...  Silicon photonics has emerged as a promising CMOS-compatible alternative to realize a new generation of deep learning accelerators that can use light for both communication and computation.  ...  Different wavelengths in a waveguide represent the input signals to the neuron. Weights are reconfigured by tuning the MRs, so that the characteristics of a specific wavelength are modified.  ... 
arXiv:2101.01751v2 fatcat:jorj4q6tjjewxfkbbovnxvpdyi

2019 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 66

2019 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
., +, TCSI March 2019 897-908 Analysis of Signals via Non-Maximally Decimated Non-Uniform Filter Banks.  ...  ., +, TCSI Nov. 2019 4230-4241 A Resource-Efficient and Side-Channel Secure Hardware Implementation of Ring-LWE Cryptographic Processor.  ...  Analysis of SRAM Enhancements Through Sense Amplifier  ... 
doi:10.1109/tcsi.2020.2966967 fatcat:f663jj5g45e3peggn3gwn5jys4

On the Confidence in Bit-Alias Measurement of Physical Unclonable Functions

Florian Wilde, Michael Pehl
2019 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)  
The results prove the need for a high number of samples when the unpredictability of PUFs is tested.  ...  This work adapts a method for the calculation of confidence intervals to Bit-Alias.  ...  Encryption was implemented in a Reconfigurable Hardware (FPGA).  ... 
doi:10.1109/newcas44328.2019.8961298 dblp:conf/newcas/WildeP19 fatcat:wv67uzuqlvcmhma3nahzdrr2ta

5G: The Convergence of Wireless Communications

Raúl Chávez-Santiago, Michał Szydełko, Adrian Kliks, Fotis Foukalas, Yoram Haddad, Keith E. Nolan, Mark Y. Kelly, Moshe T. Masonta, Ilangko Balasingham
2015 Wireless personal communications  
Therefore, 5G may not be a single radio access interface but rather a "network of networks".  ...  of several Gigabits per second with end-toend latency of a few milliseconds.  ...  Acknowledgments The work by Adrian Kliks has been funded by the Polish Ministry of Science and Higher Education within the status activity task Cognitive radio systems in 2015.  ... 
doi:10.1007/s11277-015-2467-2 pmid:27076701 pmcid:PMC4821549 fatcat:dcl7lklumbchvaiyl23zlzt3ma
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