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Linear programming based meta-heuristics for the weighted maximal planar graph

I H Osman, M Hasan, A Abdullah
2002 Journal of the Operational Research Society  
; maximal planar graph; models; meta-heuristics Introduction of electrical circuits in VLSI design;' graph planarization;” Given a complete undirected weighted graph, G= and automatic graph drawing** and  ...  Comparison of the meta-heuristics The LP-based meta-heuristics are compared with four other construction heuristics in terms of solution quality in Table 2 and in terms of computation requirement in Table  ... 
doi:10.1057/palgrave.jors.2601391 fatcat:pjhlpw3xavbbjm3qovi5ijh3ka

A new class of iterative Steiner tree heuristics with good performance

A.B. Kahng, G. Robins
1992 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We show that the performance ratio of our method can never be as bad as 3/2, and is in fact bounded by 4/3 on the entire class of instances where the c(MST)/c(MRST) cost ratio is exactly 3/2.  ...  Extensive performance results show a 2% to 3% wire length reduction over the best previous heuristics. We describe a number of variants and extensions, and suggest directions for further research.  ...  This is a fundamental problem in global routing and wire estimation for VLSI circuit layout, where we are interested in Steiner trees connecting the pins of a signal net.  ... 
doi:10.1109/43.144853 fatcat:ivore4ijgjeibpfezuafr3wwii

SoC Test Applications Using ACO metaheuristic [chapter]

Hong-Sik Kim, Jin-Ho An, Sungho Kang
2011 Ant Colony Optimization - Methods and Applications  
In this chapter, we try to transform several important problems in the field of SoC testing into ACO applicable ones, which are solved by the ACO meta-heuristic.  ...  Recent SoC (system on chip) design and test environments have deteriorated this trend more significantly.  ...  Using ACO Meta-heuristic www.intechopen.comAnt Colony Optimization -Methods and Applications www.intechopen.com  ... 
doi:10.5772/14824 fatcat:utbfmeenvfe7vjnveicgnvrsge

Mathematical optimization approach for facility layout on several rows

Miguel F. Anjos, Manuel V. C. Vieira
2020 Optimization Letters  
In this paper we consider the special case of multi-row layout in which all the departments are to be placed in three or more rows, and our focus is on, for the first time, solutions for large instances  ...  This algorithm is, to the best of our knowledge, the first one in the literature reporting solutions for instances with up to 100 departments.  ...  Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long  ... 
doi:10.1007/s11590-020-01621-z fatcat:ijqxkiezrzb3lfbjfzpodugqry

Area-Power-Temperature Aware AND-XOR Network Synthesis Based on Shared Mixed Polarity Reed-Muller Expansion

Apangshu Das, Department of ECE, National Institute of Technology Agartala, Agartala, 799046, India, Sambhu Nath Pradhan
2018 International Journal of Intelligent Systems and Applications  
As power-density is directly converging into temperature, it emerges as a challenge in front of the VLSI design engineer to minimize the effect of temperature by reducing power-density.  ...  Genetic algorithm is (a non-exhaustive heuristic algorithm) used to select the polarity of the input variable for maximum sharing.  ...  So, thermal-aware techniques can be introduced in the higher level of VLSI design (like logic or behavioral level) to improve the power and thermal characteristics of integrated circuits.  ... 
doi:10.5815/ijisa.2018.12.04 fatcat:fzjimsfkhbfrxahhayslblhav4

An Improved Adaptive Genetic Algorithm for Two-Dimensional Rectangular Packing Problem

Yi-Bo Li, Hong-Bao Sang, Xiang Xiong, Yu-Rou Li
2021 Applied Sciences  
Compared with some recent algorithms, this algorithm, which can be increased by up to 1.6604% for the average filling rate, has great significance for improving the quality of work in fields such as packing  ...  The computational results of a wide range of benchmark instances from zero-waste to non-zero-waste problems show that the HAGA outperforms those of two adaptive genetic algorithms from the related literature  ...  The experimental result data is calculated by applying the algorithm of this paper to the test source data. Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/app11010413 fatcat:totvphehljby7lobrzesxdfk4q

Further Research on Node Based Bottleneck Improvement Problem for Multicut [chapter]

Xiucui Guan, Jie Su
2006 Lecture Notes in Computer Science  
Topics of interest are found in all fields of combinatorial optimization, e.g. logistics, production, scheduling, resource and operations management, flexible manufacturing, VLSI design, network design  ...  This conference gives researchers an opportunity to present their latest results and to discuss current developments and applications, besides stimulating future interactions between the members of this  ...  The p-Center problem consists in locating p facilities among a set of M possible locations and assigning N clients to them in order to minimize the maximum distance between a client and the facility to  ... 
doi:10.1007/11816157_107 fatcat:xjdnf4kesrbczoh4ilvxxixqei

More practical bounded-skew clock routing

Andrew B. Kahng, C.-W. Albert Tsao
1997 Proceedings of the 34th annual conference on Design automation conference - DAC '97  
Preliminaries Control of signal delay skew has become a dominant objective in the routing of VLSI clock distribution networks; see [13, 9] for reviews.  ...  A clock tree T G S is an embedding of the connection topology in the Manhattan plane, i.e., each internal node v 2 G is mapped to a location lv in the Manhattan plane.  ...  The combined effects of deep-submicron physics and constraintdominated designs have led to a recent trend of "constructive estimation" in place of analytic or empirical estimation.  ... 
doi:10.1145/266021.266292 dblp:conf/dac/KahngT97 fatcat:4jtho47k4ngfhie2boqsyctkse

Grasp: An Annotated Bibliography [chapter]

Paola Festa, Mauricio G.C. Resende
2002 Operations Research/Computer Science Interfaces Series  
Since 1989, numerous papers on the basic aspects of GRASP, as well as enhancements to the basic metaheuristic have appeared in the literature.  ...  optimum in the neighborhood of the constructed solution is sought.  ...  In Meta-heuristics: Theory and applications, pages 63-82. Kluwer Academic Publishers, 1996.  ... 
doi:10.1007/978-1-4615-1507-4_15 fatcat:kvaokik4m5a2bezgzzcfaqjbui

Exploring Asynchronous MMC-Based Parallel SA Schemes for Multiobjective Cell Placement on a Cluster of Workstations

Sadiq M. Sait, Ali M. Zaidi, Mustafa I. Ali, Khawar S. Khan, Sanaullah Syed
2011 The Arabian Journal for Science and Engineering  
Simulated Annealing (SA) is a popular iterative heuristic used to solve a wide variety of combinatorial optimization problems.  ...  However, depending on the size of the problem, it may have large run-time requirements. One practical approach to speed up its execution is to parallelize it.  ...  cells in the layout by the number of rows in the layout.  ... 
doi:10.1007/s13369-010-0024-6 fatcat:llrryu4yknaofokn3vwhnnfqey

Recent Advances in Graph Partitioning [chapter]

Aydın Buluç, Henning Meyerhenke, Ilya Safro, Peter Sanders, Christian Schulz
2016 Lecture Notes in Computer Science  
We survey recent trends in practical algorithms for balanced graph partitioning together with applications and future research directions.  ...  Acknowledgements We express our gratitude to Bruce Hendrickson, Dominique LaSalle, and George Karypis for many valuable comments on a preliminary draft of the manuscript.  ...  and sequential meta-heuristics.  ... 
doi:10.1007/978-3-319-49487-6_4 fatcat:4zamxcmgvfbaxndjgxv6jog6km

Recent Advances in Graph Partitioning [article]

Aydin Buluc, Henning Meyerhenke, Ilya Safro, Peter Sanders, Christian Schulz
2015 arXiv   pre-print
We survey recent trends in practical algorithms for balanced graph partitioning together with applications and future research directions.  ...  Acknowledgements We express our gratitude to Bruce Hendrickson, Dominique LaSalle, and George Karypis for many valuable comments on a preliminary draft of the manuscript.  ...  parallel and sequential meta-heuristics.  ... 
arXiv:1311.3144v3 fatcat:zmvhlkh7ynbzvm353fv22f2gnq

Power-Aware Architectural Synthesis [chapter]

Robert Dick, Niraj Jha, Li Shang
2006 The VLSI Handbook, Second Edition  
In recent years, two trends are apparent: higher levels of the design process have been automated and power consumption has become a first-order design characteristic.  ...  This trend of automating increasingly high levels of the design process continues to this day.  ... 
doi:10.1201/9781420005967.ch17 fatcat:mc5bv5ddbbchpb5uiwwwiza57q

The coming of age of (academic) global routing

Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov
2008 Proceedings of the 2008 international symposium on Physical design - ISPD '08  
Wire routing, an important step in modern VLSI design, is increasingly responsible for timing closure and manufacturability.  ...  The CAD community has witnessed remarkable improvements in speed and quality of global routing algorithms in response to the inaugural ISPD 2007 Global Routing Contest, where prizes were awarded for best  ...  Acknowledgments The authors wish to thank Gi-Joon Nam and the ISPD 2008 steering committee for the invitation to write this paper. Dr. M. D.  ... 
doi:10.1145/1353629.1353662 dblp:conf/ispd/MoffittRM08 fatcat:t467upbwtbclvhku53xn7ooyiu

Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs

Waqar Amin, Fawad Hussain, Sheraz Anjum, Sarzamin Khan, Naveed Khan Baloch, Zulqar Nain, Sung Won Kim
2020 IEEE Access  
This paper presents the detailed comparative analysis and categorization of application mapping approaches with current trends in NoC design implementation.  ...  Moreover, the best technique identified in each category based on the evaluation of performance results. INDEX TERMS Network-on-Chip, application mapping, NoC design, VOPD, System-on-Chip.  ...  This study mainly focuses on these recent works in the field of application mapping.  ... 
doi:10.1109/access.2020.2982675 fatcat:kn6mkit3uvguvc2w6lx5dgddoe
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