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Language-driven Validation of Pipelined Processors using Satisfiability Solvers

Prabhat Mishra, Heon-mo Koo, Zhuo Huang
2005 International Workshop on Microprocessor Test and Verification  
This paper describes two practical challenges in this methodology: test generation and equivalence checking.  ...  Similarly, traditional equivalence checkers are not useful in the context of language-driven model generation and functional validation.  ...  Li-C Wang and Feng Lu of University of California, Santa Barbara for giving us the opportunity to use the Seq-SAT tool.  ... 
doi:10.1109/mtv.2005.14 dblp:conf/mtv/MishraKH05 fatcat:sdbfzkg23ngcjnyd34emg76gla

A survey of recent advances in SAT-based formal verification

Mukul R. Prasad, Armin Biere, Aarti Gupta
2005 International Journal on Software Tools for Technology Transfer (STTT)  
Dramatic improvements in SAT solver technology over the last decade, and the growing need for more efficient and scalable verification solutions have fueled research in verification methods based on SAT  ...  This paper presents a survey of the latest developments in SAT-based formal verification, including incomplete methods such as bounded model checking, and complete methods for model checking.  ...  Section 2 briefly reviews the SAT problem, basic SAT algorithms and advanced features of modern SAT solvers, and model checking.  ... 
doi:10.1007/s10009-004-0183-4 fatcat:d6hub3n6uzezhkl7dnneh2glgu

Formal Methods Group ETH Zürich

Armin Biere, Cyrille Artho, Malek Haroud, Viktor Schuppan
2003 Electronical Notes in Theoretical Computer Science  
In this short note we give an overview on past and ongoing projects in the context of formal methods for industrial critical systems of the Formal Methods Group of the Computer Systems Institute at ETH  ...  SAT and QBF The success of bounded model checking [6] relies on powerful SAT solvers. In our group we have been working on several state-of-the-art SAT solvers.  ...  Model Checking Probably the most successful approach in formal verification in recent years is model checking [8] .  ... 
doi:10.1016/s1571-0661(04)80828-4 fatcat:xaqhtrz3nzdo5ilzejoaqpah7q

SAT-solving in practice

Koen Claessen, Niklas Een, Mary Sheeran, Niklas Sorensson
2008 2008 9th International Workshop on Discrete Event Systems  
In this tutorial paper, we show briefly how such SAT-solvers are implemented, and point to some typical applications of them.  ...  It is of practical interest because modern SAT-solvers can be used to solve many important and practical problems.  ...  taking the initiative to include a special session on SAT at the International Workshop on Discrete Event Systems, May, 2008.  ... 
doi:10.1109/wodes.2008.4605923 fatcat:c3w2p5n2ena33aozdweue4eklq

Some recent advances in automated analysis

Erika Ábrahám, Klaus Havelund
2015 International Journal on Software Tools for Technology Transfer (STTT)  
In the last decade, active research in the formal methods community brought interesting results and valuable tools.  ...  We briefly outline some recent trends, and review some of the latest achievements, introducing six papers selected from the 20th International Conference on Tools and Algorithms for the Construction and  ...  We are grateful to all authors for their contributions and to the reviewers of TACAS'14 and of this special issue for their thorough and valuable work.  ... 
doi:10.1007/s10009-015-0403-0 fatcat:hwu7b64kh5brrlm7spzyucxibe

SAT-Based Verification Methods and Applications in Hardware Verification [chapter]

Aarti Gupta, Malay K. Ganai, Chao Wang
2006 Lecture Notes in Computer Science  
Verification methods based on Boolean Satisfiability (SAT) have emerged as a promising alternative to BDD-based symbolic model checking methods.  ...  We also describe practical experiences with these methods implemented in our verification platform called VeriSol (formerly DiVer), which has been used successfully in industry practice.  ...  help in applying them in an industry context.  ... 
doi:10.1007/11757283_5 fatcat:5kb2pmlvjvat5ljeei2fflzufa

Formal Methods for Functional Verification [chapter]

Randal E. Bryant, James H. Kukula
2003 The Best of ICCAD  
SAT solvers have now supplanted BDDs for many EDA applications where simple Boolean operations are required. SAT checking has recently flourished as a research area.  ...  Significant advances and fresh applications in dynamic search approaches such as SAT and automatic test pattern generation (ATPG) algorithms have paralleled those in BDDs.  ... 
doi:10.1007/978-1-4615-0292-0_1 fatcat:t776pq6t7reyffs327dkmonjse

WoLFram- A Word Level Framework for Formal Verification

André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler
2009 2009 IEEE/IFIP International Symposium on Rapid System Prototyping  
A wide range of applications is implemented, e.g. equivalence and property checking including algorithms for coverage/property analysis, debugging and robustness checking.  ...  Verification methods originally based on Boolean satisfiability (SAT) can directly benefit from this progress.  ...  Acknowledgment The techniques described here have been developed in the research projects Herkules (contract no. 01 M 3082) and VerisoftXT (contract no. 01 IS 07008 C) funded by the German Federal Ministry  ... 
doi:10.1109/rsp.2009.21 dblp:conf/rsp/SulflowKFGD09 fatcat:6umh7p3qtjhg7onwlcvdb44dfe

From Propositional Satisfiability to Satisfiability Modulo Theories [chapter]

Hossein M. Sheini, Karem A. Sakallah
2006 Lecture Notes in Computer Science  
Leveraging the advances made in SAT solvers in the past decade, we introduce several SAT-based SMT solving methods that in many applications have outperformed classical decision methods.  ...  Aside from the classical method of translating the SMT formula to a purely Boolean problem, in recent methods, a SAT solver is utilized to serve as the "glue" that ties together the different theory atoms  ...  Acknowledgement This work was funded in part by the National Science Foundation (NSF) under ITR grant No. 0205288.  ... 
doi:10.1007/11814948_1 fatcat:whtcmi5hejd7jf3ome2vhi64gi

Functional Test Generation Using Constraint Logic Programming [chapter]

Zhihong Zeng, Maciej Ciesielski, Bruno Rouzeyre
2002 IFIP Advances in Information and Communication Technology  
Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation.  ...  The experimental results are quite encouraging compared with classical CNF-based, BDD-based, and LP-based SAT solvers.  ...  It is also worthy to investigate the applications of our CLP-based SAT solver for other verification purposes, such as equivalence checking and counterexample finding in modeling checking. 7.  ... 
doi:10.1007/978-0-387-35597-9_32 fatcat:uhmy4a7uxrgbnj2tq2eaiepclq

SMT(CLU): A Step toward Scalability in System Verification

Hossein Sheini, Karem Sakallah
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
This logic is well suited for equivalence checking of two versions of a hardware design or the input and output of a compiler and has been recently utilized in several model checkers.  ...  Finally, we empirically demonstrate the effectiveness of our SMT(CLU) procedure and compare its performance to recent solvers on a wide range of hardware verification benchmarks.  ...  SAT-based Decision Methods for CLU With the recent advances in SAT solvers, several SMT approaches to solve verification problems involving integer atoms and uninterpreted functions such as CLU formulas  ... 
doi:10.1109/iccad.2006.320088 fatcat:x3skvgucizgznloezfycesxkfm

F-Soft: Software Verification Platform [chapter]

F. Ivančić, Z. Yang, M. K. Ganai, A. Gupta, I. Shlyakhter, P. Ashar
2005 Lecture Notes in Computer Science  
We thank Srihari Cadambi, Aleksandr Zaks and Himanshu Jain for their help in development of the F-Soft platform.  ...  Its novelty lies in the combination of several recent advances in formal verification research including SAT-based verification, static analyses and predicate abstraction.  ...  These resulted in considerable time savings in verification using both BDD-based and SAT-based methods.  ... 
doi:10.1007/11513988_31 fatcat:iccykpbmeveg7mdikkvsnqdjwy

SMT(CLU)

Hossein M. Sheini, Karem A. Sakallah
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
This logic is well suited for equivalence checking of two versions of a hardware design or the input and output of a compiler and has been recently utilized in several model checkers.  ...  Finally, we empirically demonstrate the effectiveness of our SMT(CLU) procedure and compare its performance to recent solvers on a wide range of hardware verification benchmarks.  ...  SAT-based Decision Methods for CLU With the recent advances in SAT solvers, several SMT approaches to solve verification problems involving integer atoms and uninterpreted functions such as CLU formulas  ... 
doi:10.1145/1233501.1233680 dblp:conf/iccad/SheiniS06 fatcat:uk7m5yp7gfepvioxekouu3gdyy

SAT-based abstraction refinement for programmable logic controllers

Sebastian Biallas, Jorg Brauer, Stefan Kowalewski
2011 2011 3rd International Workshop on Dependable Control of Discrete Systems  
Since elegant ideas and careful engineering have advanced SAT solvers to the state they can rapidly decide satisfiability of structured problems that involve thousands of variables, this approach scales  ...  well in practice.  ...  The work of Jörg Brauer was, in part, supported by the DFG Research Training Group 1298 Algorithmic Synthesis of Reactive and Discrete-Continuous Systems (AlgoSyn).  ... 
doi:10.1109/dcds.2011.5970325 fatcat:y3wdmay3wrbqfbtdcs6lezixim

Analog and Mixed-Signal Verification Using Satisfiability Solver on Discretized Models

Henry Selvaraj, Nikita Ramesh Wanjale
2017 2017 25th International Conference on Systems Engineering (ICSEng)  
However, it requires advanced mathematics knowledge and thus is not feasible for all applications.  ...  The iii verification problem is first defined using the state space equations for the given circuit and applying Satisfiability Modulo Theories (SMT) solver to determine a region that encloses complete  ...  State space exploration method can further be divided in: Equivalence and model checking . Equivalence checking method analyzes the functional equivalency of two models of the same circuit.  ... 
doi:10.1109/icseng.2017.10 dblp:conf/icseng/SelvarajW17 fatcat:xql7w557o5ckvo3qerk4siqvqi
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