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Formal verification of VHDL using VHDL-like ACL2 models [chapter]

Dominique Borrione, Philippe Georgelin
2001 Electronic Chips & Systems Design Languages  
We define the semantics of VHDL data types and behavioral-style statements in the logic.  ...  We propose to introduce mechanically supported formal reasoning in the design flow, by producing a model of VHDL behavioral specifications in the logic of the ACL2 theorem prover.  ...  Acknowledgements: The authors are thankful to Vanderlei Moraes Rodrigues for fruitful discussions and helpful comments on a previous version of this paper. References  ... 
doi:10.1007/978-1-4757-3326-6_23 fatcat:ndvyegcjmbftnpozdurmxljsmi

VHDL & Verilog compared & contrasted---plus modeled example written in VHDL, Verilog and C

Douglas J. Smith
1996 Proceedings of the 33rd annual conference on Design automation conference - DAC '96  
The second part contains a worked example of a model that computes the Greatest Common Divisor (GCD) of two numbers. The GCD is modeled at the algorithmic level in VHDL,  ...  The first part takes an unbiased view of VHDL and Verilog by comparing their similarities and contrasting their diffrences.  ...  A model with a signal whose type is one of the net data types has a corresponding electrical wire in the implied modeled circuit.  ... 
doi:10.1145/240518.240664 dblp:conf/dac/Smith96 fatcat:m7tdcmeynzexpe5i4wojd7yucy

Configurable system simulation model build comprising packaging design data

H.-W. Anderson, H. Kriese, W. Roesner, K.-D. Schubert
2004 IBM Journal of Research and Development  
But before we can build the simulation models, we need to find answers to many questions and to specify constraints, such as the scope of the simulation, the representation of the packaging data, the handling  ...  This paper discusses these new concepts in eServer development: a configurable simulation model build, the automatic derivation of structural model data from packaging design, and the addition of specific  ...  Generating system structure data from package design data For the logical verification of a system, the chips and their signal interconnects across the packaging components are modeled for logic simulation  ... 
doi:10.1147/rd.483.0367 fatcat:seslo5hnxjf2xbokecsjl73tby

Impact of Description Language, Abstraction Layer, and Value Representation on Simulation Performance

Wolfgang Ecker, Volkan Esen, Lars Schonberg, Thomas Steininger, Michael Velten, Michael Hull
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
As part of the ongoing re-work modeling language strategies and the world wide introduction of TLM, a detailed analysis of the impact of description languages, abstraction layers and data types on simulation  ...  For the presented analysis, we considered five designs that have been modeled in VHDL, Verilog, SystemVerilog, and SystemC, using different value representations and coding styles, covering the abstraction  ...  The following representations have been evaluated: • Since VHDL does not possess a built-in logic type with meta values the data types defined in the package ieee.std_logic1164 is used. o Both, the unresolved  ... 
doi:10.1109/date.2007.364688 dblp:conf/date/EckerESSVH07 fatcat:ntq7va7lezdu7hc536ge4am54e

Design, Development and Implementation of ALU, RAM and ROM for 8051 Microcontroller on FPGA using VHDL

Siddalingesh S.Navalgund, Prakash R. Tonse
2013 International Journal of Computer Applications  
Reconfigurable systems offer a solution to solve complex problems by combining the speed of hardware with the flexibility of software to improve performance and system performance.  ...  The first author specially thanks TEQIP 1.2 for providing the teaching/research assistantship for the period of March-2013 to July-2013.  ...  The authors thank the authorities of Sri Dharmasthala Manjunatheshwara College of Engineering and Technology, Dhavalagiri, Dharwad, Karnataka, India for encouraging us to carry out this research work.  ... 
doi:10.5120/13823-1280 fatcat:hnkkpo2bmjflxh2zn6pxaajj4e

Model Checking VHDL with CV [chapter]

David Déharbe, Subash Shankar, Edmund M. Clarke
1998 Lecture Notes in Computer Science  
We have completed an initial release of the VHDL model checker and have used it to verify complex circuits, including the control logic of a commercial RISC microprocessor.  ...  This article describes a prototype implementation of a symbolic model checker for a subset of VHDL.  ...  Declarations: Signal (input, output and local), variable, constant and type declarations. Types: Enumerated types.  ... 
doi:10.1007/3-540-49519-3_33 fatcat:h6da2poqp5f3bgo4bdpzdpu4da

Static Analysis of VHDL Source Code: the SAVE Project [chapter]

Mirella Mastretti, Maria Laura Busi, Roberto Sarvello, Maurizio Sturlesi, Sergio Tomasello
1996 Achieving Quality in Software  
While the typical VHDL-based design environment provides tools for code simulation and logic synthesis, no support is given in order to cope with the increasing complexity of VHDL descriptions and the  ...  VHDL (Very High Speed Integrated Circuits Hardware Description Language) is one of the most popular languages (IEEE standard) for building software models of hardware systems.  ...  VHDL allows to describe the functionalities of design components (like memory cells, chips, logic ports and so on) in an algorithmic way without assumptions about the technology of a device or the methodology  ... 
doi:10.1007/978-0-387-34869-8_11 fatcat:t4b3tove7nendphzh6w4mjybje

Design of FPGA Based Neural Network Controller for Earth Station Power System

Hanaa T. El-Madany, Faten H. Fahmy, Ninet M. A. El-Rahman, Hassen T. Dorrah
2012 TELKOMNIKA (Telecommunication Computing Electronics and Control)  
VHDL code has been proposed to implement ANNs as well as to present simulation results with floating point arithmetic of the earth station and the satellite power systems using ModelSim® PE 6.6 simulator  ...  To implement the neural network into hardware design, it is required to translate generated model into device structure. VHDL language is used to describe those networks into hardware.  ...  The STD_LOGIC_1164 is used a standard IEEE package in the NNC design which allows to use the data types (STD_LOGIC and STD_LOGIC_VECTOR) in design and basic arithmetic operations.  ... 
doi:10.12928/telkomnika.v10i2.49 fatcat:qj5xgl3obzbivig5puoc3pvkrq

Using VHDL for board level simulation

S. Habinc, P. Sinander
1996 IEEE Design & Test of Computers  
This allows ESA or another company to verify the functionality. (For more about ESA and its choice of VHDL, see the box.)  ...  A logical follow-on activity to using VHDL modeling for ASIC design verification is to model and simulate complete board designs.  ...  Acknowledgments Although not mentioned by name, we thank those companies we worked with that performed the basic work referenced in this article.  ... 
doi:10.1109/54.536097 fatcat:fcxdbpo4rjejxlz5yzaoavylca

Design of FPGA Based Neural Network Controller for Earth Station Power System

Hanaa T. El-Madany, Faten H. Fahmy, Ninet M. A. El-Rahman, Hassen T. Dorrah
2012 TELKOMNIKA (Telecommunication Computing Electronics and Control)  
VHDL code has been proposed to implement ANNs as well as to present simulation results with floating point arithmetic of the earth station and the satellite power systems using ModelSim® PE 6.6 simulator  ...  To implement the neural network into hardware design, it is required to translate generated model into device structure. VHDL language is used to describe those networks into hardware.  ...  The STD_LOGIC_1164 is used a standard IEEE package in the NNC design which allows to use the data types (STD_LOGIC and STD_LOGIC_VECTOR) in design and basic arithmetic operations.  ... 
doi:10.12928/telkomnika.v10i2.796 fatcat:zmnewsvpbzghpkgrvmm7rorkuy

Design of FPGA Based Neural Network Controller for Earth Station Power System

Hanaa T. El-Madany, Faten H. Fahmy, Ninet M. A. El-Rahman, Hassen T. Dorrah
2012 TELKOMNIKA Indonesian Journal of Electrical Engineering  
VHDL code has been proposed to implement ANNs as well as to present simulation results with floating point arithmetic of the earth station and the satellite power systems using ModelSim® PE 6.6 simulator  ...  To implement the neural network into hardware design, it is required to translate generated model into device structure. VHDL language is used to describe those networks into hardware.  ...  The STD_LOGIC_1164 is used a standard IEEE package in the NNC design which allows to use the data types (STD_LOGIC and STD_LOGIC_VECTOR) in design and basic arithmetic operations.  ... 
doi:10.11591/telkomnika.v10i2.681 fatcat:y5eohf4tqnebvm42ciug4b6uyi

FASTBUS simulation tools

T.D. Dean, M.J. Haney
1992 IEEE Transactions on Nuclear Science  
The model is written in the IEEE std 1076-1987 hardware description language VHDL. A model of the ATC logic is also presented.  ...  The high level command language is based on the FASTBUS standard routines listed in IEEE std 1177-1989.  ...  As a language, VHDL supports user defined logic types which can have user defined logic values, typically "0" and "1" for true and false, "X" for unknown, etc.  ... 
doi:10.1109/23.159731 fatcat:nrikaj3zyrb2bcm54o3cxb27hi

RT-level ITC'99 benchmarks and first ATPG results

F. Corno, M.S. Reorda, G. Squillero
2000 IEEE Design & Test of Computers  
The developed benchmarks share the characteristics of typical synthesizable blocks, are available as both RTL VHDL descriptions and gate level netlists, and allow the evaluation of the quality of test  ...  Exploiting these benchmarks, we analyzed the effectiveness of a prototypical ATPG tool (called ARTIST) suitable to generate test sequences starting from synthesizable RT-level VHDL descriptions.  ...  No VHDL packages are used, except IEEE standard logic and arithmetic ones. The code is in prevalence behavioral, with one or more concurrent processes, but some circuits also contain structural code.  ... 
doi:10.1109/54.867894 fatcat:m7al3e3xnneo3egscjhj75iquu

A Design of AMBA AXI4-Lite ACE Interconnect Protocol for Transactionbased SoC Design Techniques Integration

Chiranjeet Kumar, Dr. M. Gurunadha Babu
2017 International Journal Of Engineering And Computer Science  
Transaction-level modeling (TLM) is a technique used to describe the system by using the standard function calls which defines all the transactions which are required to verify the functionality of the  ...  The usage of the transaction based techniques are designed for the software analysis and for the first time, in this research work it is used for the physical hardware design and its analysis based on  ...  The master sends the last data item, the WLAST signal goes HIGH.  ... 
doi:10.18535/ijecs/v6i6.53 fatcat:mkm5atrxlrejjbhjzhud3vtjua

Kernel Ada to unify hardware and software design

Sy Wong, Gertrude Levine
1998 Proceedings of the 1998 annual ACM SIGAda international conference on Ada - SIGAda '98  
One important circuit design principle is to minimize signal inversions in a chain of logic elements.  ...  We request that SIGAda form a subgroup for the standardization of Kernel Ada. - - - Specification for a dual ranked flip-flop with HDL; package DFF is type device_state is limited private; type device  ... 
doi:10.1145/289524.289529 dblp:conf/sigada/WongL98 fatcat:totua4unfze2le7jd7qf6fl33a
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