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A prototype framework for knowledge-based analog circuit synthesis

R. Harjani, R. A. Rutenbar, L. R. Carley
1987 24th ACM/IEEE conference proceedings on Design automation conference - DAC '87  
Analog circuit topologies are represented as a hierarchy of functional blocks; a planning mechanism is introduced to translate performance specifications between levels in this circuit hierarchy.  ...  of the a.pproach.  ...  System-level designs, such as analog-to digital (A/D) or digital-to-analog (D/A) converters are composed of common functional blocks, performing analog functions such as amplification, sample-and-hold,  ... 
doi:10.1145/37888.37894 dblp:conf/dac/HarjaniRC87 fatcat:cqasvftw25c6haojlb5zvgk7im

A prototype framework for knowledge-based analog circuit synthesis

R. Harjani, R. A. Rutenbar, L. R. Carley
1988 Papers on Twenty-five years of electronic design automation - 25 years of DAC  
Analog circuit topologies are represented as a hierarchy of functional blocks; a planning mechanism is introduced to translate performance specifications between levels in this circuit hierarchy.  ...  of the a.pproach.  ...  System-level designs, such as analog-to digital (A/D) or digital-to-analog (D/A) converters are composed of common functional blocks, performing analog functions such as amplification, sample-and-hold,  ... 
doi:10.1145/62882.62956 fatcat:u4rn5deo7nedfk4nw24bh4lksi

Realization of dynamic range controllers on a digital signal processor for audio systems

Shugang Wei, Kensuke Shimizu, Ming Zhang
1995 Journal of the Acoustical Society of Japan (E)  
This paper describes a new design method of dynamic range controllers, such as compressor, limiter, expander and noise gate, on a DSP for digital audio systems.  ...  The digital signal processing on DSP is about 130 steps for the compressor, and 120 steps for the expander with a given expansion ratio equal to or smaller than 15.  ...  If such analog dynamic range controllers were used in a digital audio system , the digital-to-analog and analog-to-digital converters have to be used, which must increase the cost and complexity of the  ... 
doi:10.1250/ast.16.353 fatcat:ctrnhuhf6resjfa6xxio43yuiq

Page 26 of SMPTE Motion Imaging Journal Vol. 87, Issue 1 [page]

1978 SMPTE Motion Imaging Journal  
Approximate costs for the analog and digital version of this function are about $8 and $60 respectively. Figure 13 illustrates a digital comb fil- ter.  ...  While reasonably simple operations, such as gain control, are less costly to implement in analog form, digital techniques show a MULTIPLIER oe ones our 8 BIT CONTROL WworRD FROM EXT SWITCH OR A/D Fig.  ... 

A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits

M.M. Hafed, N. Abaskharoun, G.W. Roberts
2002 IEEE Journal of Solid-State Circuits  
The core consists of a completely digital implementation, except for a simple reconstruction filter and a comparator.  ...  It is capable of both generating arbitrary band-limited waveforms (for excitation purposes) and coherently digitizing arbitrary periodic analog waveforms (for DSP-based test and measurement).  ...  system-level abstractions while simultaneously dealing with physical effects at the transistor and parasitic levels [1] .  ... 
doi:10.1109/4.991388 fatcat:w4m55qus2vbz3hgmg4n3feidtm

Digitally enhanced analog circuits: System aspects

Boris Murmann, Christian Vogel, Heinz Koeppl
2008 2008 IEEE International Symposium on Circuits and Systems  
An overview of digital enhancement techniques for analog circuits is presented.  ...  analog blocks.  ...  Digital enhancements of analog and mixed signal functions can be classified into system-level and block-level schemes.  ... 
doi:10.1109/iscas.2008.4541479 dblp:conf/iscas/MurmannVK08 fatcat:b3v76rljdfcr5hclzcqdspoyce

Mixed-signal PI controller in current-mode DC-DC buck converter for automotive applications

Yasser Moursy, Raouf Khalil, Sergio Lecce, Vanni Poletto, Ramy Iskander, Marie-Minerve Louerat
2016 2016 IEEE International Symposium on Circuits and Systems (ISCAS)  
The digital part is synthesized with HDL coder and laid-out using 0.35 µm CMOS technology. The estimated silicon area of the proposed solution is about 0.1 mm 2 .  ...  Simulink is used to model the proposed DC-DC buck converter on the system level. The proposed system is verified by full system level simulation.  ...  Besides, the implementation of Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) at such high frequency is power hungry solution.  ... 
doi:10.1109/iscas.2016.7538873 dblp:conf/iscas/MoursyKLPIL16 fatcat:cqmnzepyrnfwbht3xg7bn5etoq

Foundations of computational neuroscience

Gualtiero Piccinini, Oron Shagrir
2014 Current Opinion in Neurobiology  
conventional, observer-dependent description; and how computational descriptions and explanations are related to other levels of analysis and organization.  ...  We discuss foundational issues such as what we mean by 'computation' and 'information processing' in nervous systems; whether computation and information processing are matters of objective fact or of  ...  There is a debate about the role of the computational level and how it relates to the algorithmic and the implementation levels.  ... 
doi:10.1016/j.conb.2013.10.005 pmid:24709597 fatcat:wyvfbzqa6jcxdl6ledokhs7hcm

DESIGN, IMPLEMENTATION AND ANALYSIS OF FLASH ADC ARCHITECTURE WITH DIFFERENTIAL AMPLIFIER AS COMPARATOR USING CUSTOM DESIGN APPROACH

CHANNAKKA LAKKANNAVAR, SHRIKANTH K. SHIRAKOL, KALMESHWAR N. HOSUR
2012 International Journal of Electronics Signals and Systems  
The integrated flash ADC is operated at 4-bit precision with analog input voltage of 0 to 1.8V.  ...  analog signal and the digital signal processors.  ...  However, "CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters", 2 nd Edition, 2005 by Rudy J. van de Plassche et al, deals with the evolution of technology has not provided same level of  ... 
doi:10.47893/ijess.2012.1065 fatcat:unwbvn57ona2dkm3pdqrkj24dq

Applying models in your testing process

S Rosaria, H Robinson
2000 Information and Software Technology  
Model-based testing allows large numbers of test cases to be generated from a description of the behavior of the system under test.  ...  Given the same description and test runner, many types of scenarios can be exercised and large areas of the application under test can be covered, thus leading to a more effective and more efficient testing  ...  This in turn makes it possible to implement oracles of any level of sophistication.  ... 
doi:10.1016/s0950-5849(00)00125-7 fatcat:a4ujnkmx3zfvzie5qrfmbspu7u

A Mixed-Signal Embedded Platform for Automotive Sensor Conditioning

Emilio Volpi, Luca Fanucci, Adolfo Giambastiani, Alessandro Rocchi, Francesco D'Ascoli, Marco Tonarelli, Massimiliano Melani, Corrado Marino
2010 EURASIP Journal on Embedded Systems  
Such platform consists in a wide set of optimized high-performance analog, digital, and software intellectual property (IP) modules for various kinds of sensors.  ...  Some case examples are presented to demonstrate the effectiveness and flexibility of this system.  ...  EURASIP Journal on Embedded Systems (b) System Level Design: this solution [4, 5] is based on a high-level language such as SystemC used to describe HW/SW systems at multiple levels of abstraction and  ... 
doi:10.1155/2010/945646 fatcat:yvl6wdkn5bdjvknha7d4trhfkq

Digital-to-analog converter with gamma correction on glass substrate for TFT-panel applications

Tzu-Ming Wang, Yu-Hsuan Li, Ming-Dou Ker
2009 Journal of the Society for Information Display  
In this work, a 6-bit R-string digital-to-analog converter (DAC) with gamma correction on glass substrate for TFTpanel applications is proposed.  ...  The area of the new proposed DAC circuit is effectively reduced to about one-sixth compared to that of the conventional circuit for the same LTPS process.  ...  Acknowledgment This work was supported by AU Optronics Corp. and particularly supported by the "Aim for the Top University Plan" of National Chiao Tung University and Ministry of Education, Taiwan, R.O.C  ... 
doi:10.1889/jsid17.10.785 fatcat:4oomafwnxfhqljjkhkhfoblgry

Beyond Formal Structure: A Mechanistic Perspective on Computation and Implementation

Marcin Miłkowski
2011 Journal of Cognitive Science  
In this article, after presenting the basic idea of causal accounts of implementation and the problems they are supposed to solve, I sketch the model of computation preferred by Chalmers and argue that  ...  I also argue that it does not suffice to replace Chalmers' favorite model with a better abstract model of computation; it is necessary to acknowledge the causal structure of physical computers that is  ...  For this reason, a philosophical account of implementation should remain neutral in the discussion over modeling computational systems on the level of behavioral equivalence.  ... 
doi:10.17791/jcs.2011.12.4.361 fatcat:xccjs4piizfbvaf4nrlj6n7cm4

Using codesign techniques to support analog functionality

Francis G. Wolff, Michael J. Knieser, Dan J. Weyer, Chris A. Papachristou
1999 Proceedings of the seventh international workshop on Hardware/software codesign - CODES '99  
This paper describes some of the design implementation partitioning issues and experiences using analog and digital techniques for embedded systems.  ...  With the growth of System on a Chip (SoC), the functionality of analog components must also be considered in the design process.  ...  This allows for a higher level exploration of the analog and digital codomains in the design before components are implemented.  ... 
doi:10.1145/301177.301492 dblp:conf/codes/WolffKWP99 fatcat:xoq3iuo53bd55gfcubp6bqdz5m

The Belle trigger system with the new silicon vertex detector SVD 2.0

T. Ziegler
2003 2003 IEEE Nuclear Science Symposium. Conference Record (IEEE Cat. No.03CH37515)  
In addition a new hardware trigger Level 1.5 was 1111 Riken designed and installed which takes advantage of the digitized SVD hit data.  ...  The resulting improvement in the Belle trigger system will be important to deal with the increasing luminosity and higher beam currents of the KEKB factory which will produce expected Level 1 trigger rates  ...  The analog values are then read out in series with a clock of 5 MHz and send for digitization to the FADC system.  ... 
doi:10.1109/nssmic.2003.1351927 fatcat:vf2m4p4nhnbkzdmccsjgrz2i4u
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