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Embedded block coding in JPEG2000

D. Taubman, E. Ordentlich, M. Weinberger, G. Seroussi, I. Ueno, F. Ono
2000 Proceedings 2000 International Conference on Image Processing (Cat. No.00CH37101)  
This paper describes the embedded block coding algorithm at the heart of the JPEG2000 image compression standard.  ...  The algorithm utilizes the same low complexity binary arithmetic coding engine as JBIG2.  ...  Unfortunately, none of these techniques can guarantee a high throughput rate (e.g. one sample per "clock") in each and every code-block, without excessive implementation cost.  ... 
doi:10.1109/icip.2000.899218 dblp:conf/icip/WeinbergerSUO00 fatcat:ogzd74iwwzhkda2lytka3u6tza

Architecture design of a high-performance dual-symbol binary arithmetic coder for JPEG2000

Minsoo Rhu, In-Cheol Park
2009 2009 16th IEEE International Conference on Image Processing (ICIP)  
The embedded-block coding with optimized truncation (EBCOT), which consists of a bit-plane coder (BPC) and a binary arithmetic coder (BAC), is the bottleneck in realizing a high-performance JPEG2000 encoding  ...  It enables parallel processing of the usual byte-out cases in BAC, and can achieve a throughput of 534 M symbols/sec, which is the highest compared to those of the previous BAC architectures.  ...  Since the EBCOT accounts for the majority of the computation time in JPEG2000 encoding system, a high-performance EBCOT is in demand.  ... 
doi:10.1109/icip.2009.5414131 dblp:conf/icip/RhuP09 fatcat:qqyf4tjfv5b2njcadf622k6mj4

A hybrid dual-core Reconfigurable Processor for EBCOT tier-1 encoder in JPEG2000 on next generation of digital cameras

Xin Zhao, Ahmet T. Erdogan, Tughrul Arslan
2010 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)  
In addition, this hybrid processor also shows its high potential for implementing the complete JPEG2000 encoder on it targeting next generation of camera applications.  ...  In this paper, we present a JPEG2000 EBCOT tier-1 encoder based on a hybrid dual-core processor composed of a coarsegrained Dynamically Reconfigurable Processor (DRP) and an ARM core targeting next generation  ...  Cho et al. in [4] presented a JPEG2000 encoder implemented on TMS320C6416 with an improvement on the cache hit ratio, however the throughput obtained is also low with consideration to their high-end  ... 
doi:10.1109/dasip.2010.5706250 dblp:conf/dasip/ZhaoEA10 fatcat:knomkytpcffofpj46iwdvobu2i

Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding

John M. McNichols, Eric J. Balster, William F. Turri, Kerry L. Hill
2013 International Journal of Reconfigurable Computing  
The Altera NIOS II processor is chosen for the implementation and is coupled with existing embedded processing modules to realize a fully embedded JPEG2000 encoder.  ...  While most of the research in this field centers on acceleration of the EBCOT Tier I encoder, this work focuses on an embedded solution for EBCOT Tier II.  ...  Conclusions The objective of this thesis is to realize a fully embedded JPEG2000 encoder on an FPGA.  ... 
doi:10.1155/2013/140234 fatcat:kfurlpia3vdfzjscybzazihfyq

Optimizing JPEG2000 Still Image Encoding on the Cell Broadband Engine

Seunghwa Kang, David A. Bader
2008 2008 37th International Conference on Parallel Processing  
In this work, we optimize the computationally intensive algorithmic kernels of JPEG2000 for the Cell/B.E. and also introduce a novel data decomposition scheme to achieve high performance with low programming  ...  The Cell/B.E. demonstrates 3.2 times higher performance for lossless encoding and 2.7 times higher performance for lossy encoding.  ...  We acknowledge Georgia Institute of Technology, its Sony-Toshiba-IBM Center of Competence, and the National Science Foundation, for the use of Cell Broadband Engine resources that have contributed to this  ... 
doi:10.1109/icpp.2008.39 dblp:conf/icpp/KangB08 fatcat:72clgrshvnbi7afjodh3wuneom

Interactive Editing of GigaSample Terrain Fields

Marc Treib, Florian Reichl, Stefan Auer, Rüdiger Westermann
2012 Computer graphics forum (Print)  
To achieve high decoding and encoding throughput, we employ a compression scheme for height and pixel maps based on a sparse wavelet representation.  ...  Such applications require both decoding and encoding to be faster than disk transfer. We present a novel approach for editing gigasample terrain fields at interactive rates and high quality.  ...  Acknowledgments The authors wish to thank the Landesvermessungsamt Feldkirch, Austria, for providing the Vorarlberg data. This publication is based on work supported by Award No.  ... 
doi:10.1111/j.1467-8659.2012.03017.x fatcat:hrbrl7otybcynpimuutbfjfnni

A Survey of Image Compression Algorithms for Visual Sensor Networks

Abdelhamid Mammeri, Brahim Hadjou, Ahmed Khoumsi
2012 ISRN Sensor Networks  
In this paper, we provide a survey of image compression algorithms for visual sensor networks, ranging from the conventional standards such as JPEG and JPEG2000 to a new compression method, for example  ...  We conclude by some guidelines which concern the design of a compression method for VSN.  ...  At the end of the second tier, a compressed bitstream is generated for transmission purpose.  ... 
doi:10.5402/2012/760320 fatcat:ksg76nsh4vc5fdvfwxujzhh5ra

A Systematic Review of Hardware-Accelerated Compression of Remotely Sensed Hyperspectral Images

Amal Altamimi, Belgacem Ben Ben Youssef
2021 Sensors  
We present a comparative performance analysis of the synthesized results with an emphasis on metrics like power requirement, throughput, and compression ratio.  ...  Hyperspectral imaging is an indispensable technology for many remote sensing applications, yet expensive in terms of computing resources.  ...  Significant improvement in the throughput is realized, thereby reaching up to 18 MSps by utilizing the algorithm's high level of parallelism and low computational complexity.  ... 
doi:10.3390/s22010263 pmid:35009804 pmcid:PMC8749878 fatcat:uvhmdpurevajvoxkf23mv5ie7a

Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder

Yu-Wen Huang, Bing-Yu Hsieh, Tung-Chien Chen, Liang-Gee Chen
2005 IEEE transactions on circuits and systems for video technology (Print)  
A low cost general purpose processor cannot process these operations in real time. In this paper, we proposed two solutions for platform-based design of H.264/AVC intra frame coder.  ...  The predictor generation engine for intra prediction and the transform engine for mode decision are critical because the operations require a lot of memory access and occupy 80% of the computation time  ...  The image quality of H.264/AVC is very close to that of ratio of the encoder complexities for JPEG, JPEG2000 (DWT 53), and H.264/AVC intra frame coder (CAVLC and low complexity mode decision), respectively  ... 
doi:10.1109/tcsvt.2004.842620 fatcat:fc3mcqqjz5huvmu7b5qoevwm7u

Onboard Image Processing System for Hyperspectral Sensor

Hiroki Hihara, Kotaro Moritani, Masao Inoue, Yoshihiro Hoshi, Akira Iwasaki, Jun Takada, Hitomi Inada, Makoto Suzuki, Taeko Seki, Satoshi Ichikawa, Jun Tanii
2015 Sensors  
Onboard image processing systems for a hyperspectral sensor have been developed in order to maximize image data transmission efficiency for large volume and high speed data downlink capacity.  ...  The circuitry is embedded into the data formatter of the sensor system without adding size, weight, power consumption, and fabrication cost.  ...  The image compression method should have coding efficiency, high compression speed, and low complexity in order to reduce the mass, size, power consumption, and fabrication cost of the onboard signal processing  ... 
doi:10.3390/s151024926 pmid:26404281 pmcid:PMC4634475 fatcat:txb7tx7blnb7fdow35ntbpt53y

Underwater radio frequency image sensor using progressive image compression and region of interest

Eduardo M. Rubino, Diego Centelles, Jorge Sales, José V. Martí, Raúl Marín, Pedro J. Sanz, Alberto J. Álvares
2017 Journal of the Brazilian Society of Mechanical Sciences and Engineering  
The increasing demand for underwater robotic intervention systems around the world in several application domains requires more versatile and inexpensive systems.  ...  The paper focuses on the compression subsystem and does not attempt to improve the communications physical media for better underwater RF links.  ...  The RF transmission system is at an early stage and, for evaluation purposes, a low-power radio module has been used.  ... 
doi:10.1007/s40430-017-0894-6 fatcat:mclqt2jz6nfclbbypxhqhpdgvi

Automated Design Space Exploration for DSP Applications

Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winser Alexander
2008 Journal of Signal Processing Systems  
Our framework synthesizes designs from a high level of abstraction into well-constructed and recognizable hardware structures that perform well in terms of area, throughput and power dissipation.  ...  This reduces the architectural generation and hardware synthesis process from days to several hours for complex designs.  ...  While other tools provide one or two IP blocks for general purpose DSP applications, we provide a system that generates application specific, and therefore efficient, hardware blocks.  ... 
doi:10.1007/s11265-008-0226-2 fatcat:angbfbzirjf5fha24fcolofgzq

An On-Off Queue Control Mechanism for Scalable Video Streaming over the IEEE 802.11e WLAN

Y. Zhang, C. H. Foh, J. Cai
2008 2008 IEEE International Conference on Communications  
Specifically, we propose a distributed on-off queue control (OOQC) mechanism, which is designed to maintain high network throughput while keeping packet loss due to collision as low as possible.  ...  A low priority early drop (LPED) method is also employed to drop the packets at the queue according to packet relative priority index (RPI) provided by scalable video coding.  ...  The final video bitstream consists of the MV information generated by MCTF and the JPEG2000 bitstream for each T-band. III.  ... 
doi:10.1109/icc.2008.929 dblp:conf/icc/ZhangFC08 fatcat:6yoftj2mg5ahticc6z335wg6jq

A High-Definition H.264/AVC Intra-Frame Codec IP for Digital Video and Still Camera Applications

C.-W. Ku, C.-C. Cheng, G.-S. Yu, M.-C. Tsai, T.-S. Chang
2006 IEEE transactions on circuits and systems for video technology (Print)  
This paper presents a real-time high-definition 720p@30fps H.264/MPEG-4 AVC intra-frame codec IP suitable for digital video and digital still camera applications.  ...  The whole codec design only needs 103 K gate count for a core size of 1.28 1.28 mm 2 and achieves real-time encoding and decoding at 117 and 25.5 MHz, respectively, when implemented by 0.18-m CMOS technology  ...  The final chip implementation can achieve real-time high-defintion (HD) sized encoding and decoding with low hardware cost and operating frequency. This paper is organized as follows.  ... 
doi:10.1109/tcsvt.2006.879992 fatcat:rtuftjkahbga5llvrew5npxnui

Adaptive Low-Power Architectures for Embedded Multimedia Systems [chapter]

Muhammad Shafique, Jörg Henkel
2011 Hardware/Software Architectures for Low-Power Embedded Multimedia Systems  
Moreover, for embedded multimedia systems, the existing low-power design approaches generally tradeoff throughput and/or quality level.  ...  In this dissertation, we target high-performance in terms of low-power, highthroughput, area-efficient, and flexible digital signal processing for batterypowered multimedia embedded systems, with a case  ...  In order to provide solutions of high quality (high frame resolution, high frame rate, and low distortion) or low cost (low bit rate for storage or transmission) or both, video compression is indispensable  ... 
doi:10.1007/978-1-4419-9692-3_3 fatcat:hfcxk5zklfdodffl4hwvgurz6u
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