A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Filters
FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing
2005
EURASIP Journal on Advances in Signal Processing
Preserved Fulltext
A fieldprogrammable-gate-array-(FPGA-) based configurable systolic architecture specially tailored for real-time window-based image operations is presented in this paper. ...
The architecture reaches a throughput of 3.16 GOPs at a 60 MHz clock frequency and a processing time of 8.35 milliseconds for 7 × 7 generic window-based operators on 512 × 512 gray-level images. ...
From Figure 9 , it can be shown that it is possible to achieve real-time performance for window-based image processing with very compact architectures. ...
doi:10.1155/asp.2005.1024
fatcat:ubpgy5vh7bfhnpywnfilbe2dna
Real-time stereo matching architecture based on 2D MRF model: a memory-efficient systolic array
2011
EURASIP Journal on Image and Video Processing
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Our architecture records 19 times smaller memory than the global minimization technique, which is a principal step toward real-time chip implementation of the various iterative image processing algorithms ...
Remarkable memory saving can be obtained with our memory reduction scheme, and our new architecture is a systolic array. ...
For a real-time application with small and compact hardware, GPU-and CPU-based system is not good due to their bulky size. ...
doi:10.1186/1687-5281-2011-4
fatcat:m2qojiricfg7nltfhux5krqy2e
FPGA Based Acceleration for Image Processing Applications
[chapter]
2009
Image Processing
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
The final section will show how to implement the hardware design based on the SoC or FPGA to accelerate image processing. ...
Subsequently, the application of image processing for the special eye examination and a newly three-dimensional digital camera are introduced. ...
640×480
868.51 ms
322 Gλ 2
(Torres-Huitzil,
2003)
Systolic
FPGA-based
7×7 Generic
Window-based
Image operator
640×480
9.7 ms
15 Gλ 2
(Vega-
Rodriguez, 2002)
Systolic
FPGA-based ...
doi:10.5772/7067
fatcat:k25gjbmimzgb3hfztxxgkozm6q
FPGA Implementation of the Pixel Purity Index Algorithm for Remotely Sensed Hyperspectral Image Analysis
2010
EURASIP Journal on Advances in Signal Processing
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
real-time requirements. ...
Experimental results reveal that the proposed hardware system is easily scalable and able to provide accurate results with compact size in (near) real-time, which make our reconfigurable system appealing ...
a real-time response in remote sensing applications with real-time requirements. ...
doi:10.1155/2010/969806
fatcat:snt3et7hevhd7clk7hbuozoegi
Clusters Versus FPGA for Parallel Processing of Hyperspectral Imagery
2008
The international journal of high performance computing applications
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Hyperspectral imaging is a new technique in remote sensing that generates images with hundreds of spectral bands, at different wavelength channels, for the same area on the surface of the Earth. ...
gate array (FPGA) device. ...
architectures such as FPGAs and GPUs. ...
doi:10.1177/1094342007088376
fatcat:ii7o76cywvg35kfmcmw5zb5t7a
IMPLEMENTATION METHOD ON MEDICAL IMAGE COMPRESSION SYSTEM: A REVIEW
2017
Jurnal Teknologi
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
Medical image processing is a niche area concerned with the operations and processes of generating images of the human body for clinical purposes. ...
Potential areas such as image acquisition, image enhancement, image compression and storage, and image based visualization also include in medical image processing analysis. ...
Therefore, there is a real need for high-performance systems, whilst keeping architectures flexible to allow for quick upgradeability with real-time applications [19] , [20] . ...
doi:10.11113/jt.v79.7873
fatcat:ygxpova2xbb3zd3yweyfwgph74
A Compact CMOS Face Detection Architecture Based on Shunting Inhibitory Convolutional Neural Networks
2008
4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
In this paper, we present a compact, low cost, real-time CMOS hardware architecture for face detection. ...
Disciplines Physical Sciences and Mathematics Abstract-In this paper, we present a compact, low cost, real-time CMOS hardware architecture for face detection. ...
The proposed hardware offers a good tradeoff between detection performance and implementation complexity. To enable a low cost real-time on-chip integration, a VLSI systolic architecture was adopted. ...
doi:10.1109/delta.2008.66
dblp:conf/delta/ZhangBBB08
fatcat:u74txo57nbgafe6qnmagt7xpey
High performance computing for hyperspectral image analysis: Perspective and state-of-the-art
2009
2009 IEEE International Geoscience and Remote Sensing Symposium
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2011; you can also visit the original URL.
The file type is application/pdf.
Combined, the revision of existing techniques conducted in this paper, along with the description of performance results for a parallel hyperspectral processing chain on different architectures, delivers ...
, and specialized hardware architectures such as field programmable gate arrays (FPGAs) and graphic processing units (GPUs). ...
This introduces the need to process a full image cube (614 × 512) pixels with 224 bands in no more than 5 seconds to achieve real-time performance. ...
doi:10.1109/igarss.2009.5417729
dblp:conf/igarss/PlazaDC09
fatcat:p2y2j2lbcravrl6qia2olb6ylu
Dual Super-Systolic Core for Real-Time Reconstructive Algorithms of High-Resolution Radar/SAR Imaging Systems
2012
Sensors
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
A high-speed dual super-systolic core for reconstructive signal processing (SP) operations consists of a double parallel systolic array (SA) machine in which each processing element of the array is also ...
We show how such dual SSA core, drastically reduces the computational load of complex RS regularization techniques achieving the required real-time operational mode. ...
Thus, the processing time of the proposed dual SSA core-oriented architecture is approximately 16 times less than the corresponding processing time achievable with the conventional C++ PC-based implementation ...
doi:10.3390/s120302539
pmid:22736964
pmcid:PMC3376574
fatcat:rh3ohzgyabfvngoam3enitca6m
Subframe multiplexing for FPGA manufacturing test configuration
2004
Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays - FPGA '04
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
This limitation can be overcome with a DBM (Decoder Based Multicontext) routing architecture which introduces a decoding stage between configuration memories and routing structures, so that the number ...
For this work, an FPGA based ART extractor was designed and simulated for a Xilinx Virtex-E XCV300e in order to provide a speedup over software based extraction. ...
This paper proposes a bit-level super-systolic FIR filter with a FPGA-based bit-serial semi-systolic multiplier. ...
doi:10.1145/968280.968315
dblp:conf/fpga/Chmelar04
fatcat:bkkwooxvszbvlfrg4b7h5svtvi
Clusters versus FPGAs for spectral mixture analysis-based lossy hyperspectral data compression
2008
Satellite Data Compression, Communication, and Processing IV
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
Flight Center, and a hardware implementation developed on a Xilinx Virtex-II FPGA device. ...
Analytical and experimental results are presented in the context of a real application, using hyperspectral data collected by NASA's Jet Propulsion Laboratory over the World Trade Center area in New York ...
ACKNOWLEDGMENTS This research was supported in part by the European Commission through the Marie Curie Reseach Training Network project Hyperspectral Imaging Network (MRTN-CT-2006-035927). ...
doi:10.1117/12.798326
fatcat:ywwwk7afzvgajk7z6eri5l6rqy
Employing pipelined thinning architecture for real-time fingerprint verifier
2006
IEE Proceedings - Computers and digital Techniques
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
With the availability of fast thinning hardware, real-time image processing applications can be achieved. ...
Equipped with a modification unit array, a designated operating schedule, and an address generator based on systolic counter, this thinning processor is able to perform a thinning operation within 0.07 ...
The processing time for a 512 Â 512 image is about 0.07 s. ...
doi:10.1049/ip-cdt:20050200
fatcat:bv2xru3gwrgitne7xh6dddm7ta
Artificial neural networks in hardware: A survey of two decades of progress
2010
Neurocomputing
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2015; you can also visit the original URL.
The file type is application/pdf.
Hardware neural network Neurochip Parallel neural architecture Digital neural design Analog neural design Hybrid neural design Neuromorphic system FPGA based ANN implementation CNN implementation RAM based ...
Parallel digital implementations employing bit-slice, systolic, and SIMD architectures, implementations for associative neural memories, and RAM based implementations are also outlined. ...
Effectiveness of the proposed architecture is tested with a prototype system using FPGA board and a host computer interacting with each other using PCI bus on a real-time visual data with a time resolution ...
doi:10.1016/j.neucom.2010.03.021
fatcat:regzu6sshvekzd5wxcuaiytgqu
Dynamically reconfigurable systolic array accelerators: a case study with extended Kalman filter and discrete wavelet transform algorithms
2010
IET Computers & Digital Techniques
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
There is a need to support several complex applications for navigation and image processing in a rapidly responsive on-board FPGA-based computer. ...
This technique provided a 2.7x improvement in reconfiguration time compared to an off-chip partial reconfiguration technique that used a Flash card on the FPGA board, and a 44% improvement in BRAM usage ...
Real time responsiveness on FPGAs translates to the ability to partially and dynamically reconfigure the device in real time. ...
doi:10.1049/iet-cdt.2008.0139
fatcat:crmmlzzywrcyzhgijyqd2nzfci
General-purpose systolic arrays
1993
Computer
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Future computationally intensive applications suited for desktop computing machines include real-time text, speech, and image processing. These applications require massive parallelism.' ...
With advances in VLSI, WSI, and FPGA technologies, they have progressed from fixedfunction to generalpurpose architectures. hen Sun Microsystems introduced its first workstation, the company could not ...
Future computationally intensive applications suited for desktop computing machines include real-time text, speech, and image processing. These applications require massive parallelism.' ...
doi:10.1109/2.241423
fatcat:5pbdb7wypbbqzk7riagtv5jsvq
« Previous
Showing results 1 — 15 out of 300 results