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Read/write margin enhanced 10T SRAM for low voltage application
2016
IEICE Electronics Express
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The static random access memory (SRAM) is indispensable for high performance applications. With technology scaling, the device size as well as the operation supply voltage (VDD) is reduced. ...
The simulation results indicate that, compared with the conventional 6T SRAM, the read static noise margin (RSNM) and write margin (WM) of the proposed 10T SRAM achieve 2.43× and 4.51× improvement, respectively ...
Conclusion In this paper, a novel 10T SRAM cell with read/write margin enhanced is proposed for ultra low supply voltage. ...
doi:10.1587/elex.13.20160382
fatcat:jkaljkg4zncdxdihjzz2jreshe
An Advanced Embedded SRAM Cell with Expanded Read/Write Stability and Leakage Reduction
2012
Journal of IKEEE
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During the read operation, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level, and thus producing near-ideal voltage transfer characteristics essential for robust ...
The stability enhancement and leakage power reduction provided with the proposed bit-cell are confirmed under process, voltage and temperature variations. ...
increased
-
-
18%
reduced
∼10%
increased
45%
reduced
R e fe r en ce s margin-free SRAM cell for low-VDD and high-speed applications", IEEE Journal of Solid-State Circuits, vol. 41, pp. 113 ...
doi:10.7471/ikeee.2012.16.3.265
fatcat:zklvv72wgzfc5nwksybxmwg55m
Ultra-Low Power, Process-Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications
2017
Journal of Low Power Electronics and Applications
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Moreover, due to the schmitt triggering and read decoupling of 10T SRAM the static and dynamic behavior in read, write and standby mode has shown enhanced tolerance at different process, voltage and temperature ...
Keywords: power gating; read decoupling; read-write static noise margin; dynamic noise margin; read-write energy; schmitt trigger; leakage power. ...
Though, some of the above mentioned works on bulk-CMOS SRAMs has considered vital for power reduction, but it degrades noise margins and read-write speed. ...
doi:10.3390/jlpea7030024
fatcat:dg5i5ze3nfh7bnzfuxlxi4de7e
Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation
2021
IEEE Access
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Write ability yields and write assist voltage for the 5σ write ability yields of the bitcells.
FIGURE 19 . 19 Comparison of read, write and total operation energies. FIGURE 20. ...
INTRODUCTION Recently, the demand for a low-energy system on chip (SoC) for application in the Internet of Things (IoT), biomedical implants, and energy harvesting devices has increased significantly. ...
doi:10.1109/access.2021.3075460
fatcat:naw3vx3e3vb7hb4jvh24cdw4hy
Improving Vmin of Sram by Schmitt-Trigger/Read-Write Techniques
2013
IOSR Journal of VLSI and Signal processing
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Read and write assist techniques are now commonly used to lower the minimum operating voltage (V min ) of an SRAM. ...
In modern Trends, the demand for memory has been increases tremendously. ...
By Schmitt-Trigger/Read-Write Techniques ...
doi:10.9790/4200-0211520
fatcat:wqujrhjrfzdz5nbtl7lxgndeau
An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions
2011
2011 IEEE International SOC Conference
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The proposed SRAM-based FIFO memory also features adaptive power control circuit, counter-based pointers, and a smart replica read/write control unit. ...
In this paper, an ultra-low power (ULP) 16Kb SRAM-based first-in first-out (FIFO) memory is proposed for wireless body area networks (WBANs). ...
The proposed 10T SRAM bit-cell capable of read/write abilities enhancement is discussed in Section II. Section III describes the ultra-low power Section IV presents the simulation results. ...
doi:10.1109/socc.2011.6085069
dblp:conf/socc/DuCYH11
fatcat:dk3h26kddzffvnt3oxiifhrw2m
Static Noise Margin Enhanced in FinFET Based 10T SRAM Cell at 45 nm using EDA Tool
2016
International Journal of Computing and Digital Systems
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We can analyze the SRAM cells stability and this is done by SNM investigation in read, write and hold mode. ...
Actually for every Static Random Access Memory (SRAM) cell there is a fix Static Noise Margin (SNM) is present which shows margin of the stability in operations of the SRAM cells. ...
with collaboration of Cadence System Design for the work to be completed. ...
doi:10.12785/ijcds/050603
fatcat:ga3d2ioktbfsde7a3wg7brnmka
A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications
2021
Sensors
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An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications. ...
The proposed design not only solves the half-selected problems and increases the read static noise margin (RSNM) but also provides low leakage power performance. ...
Acknowledgments: The authors would like to acknowledge for technical support in simulation by Taiwan Semiconductor Research Institute, EDA tool support for IC implementation. ...
doi:10.3390/s21196591
pmid:34640911
fatcat:uaiv6ax6xva2flqkhpmcc2adw4
A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS
2011
IEEE/ACM International Symposium on Low Power Electronics and Design
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For the ultra-low power consideration, the primary concerns of SRAM are stability and reliability instead of performance. ...
The proposed SRAM is able to operate at a voltage as low as 0.3V. One extra virtual ground (VVSS) line is used to reduce the bit-line leakage to ensure the data can be read successfully. ...
The authors would like to thank Ministry of Education, Taiwan, R.O.C. and ITRI for their support. ...
doi:10.1109/islped.2011.5993652
fatcat:pihub5odorbctmzih4kxokrnuq
A Robust 10T SRAM Cell with Enhanced Read Operation
2015
International Journal of Computer Applications
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Therefore, the proposed 10T SRAM cell can be used where the speed and robustness are the primary requirements. General Terms High speed SRAM cell, Robust SRAM cell, Differential Read-Write SRAM cell. ...
This paper presents a new 10T SRAM cell that has enhanced read speed along with good read and write stability. ...
The proposed circuit provides a differential read through different access path for read & write operations; therefore, it utilizes a differential sensing scheme for read operation. ...
doi:10.5120/ijca2015906751
fatcat:ncvuq7rjybcx7ijastpaergkuy
Design of Area Efficient, Low-Power and Reliable Transmission Gate-based 10T SRAM Cell for Biomedical Application
2021
Maǧallaẗ al-abḥāṯ al-handasiyyaẗ
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This brief proposes the design of a Transmission gate-based SRAM cell for Bio medical application eliminating the use of peripheral circuitry during the read operation. ...
This topology offers smaller area, reduced delay, low power consumption as well as improved data stabilization in the read operation. The cell is implemented in 45nm CMOS technology operated at 0.45V. ...
SRAMs usually operate in three states namely Read, Write and Hold (Abhishek et al., 2014) . ...
doi:10.36909/jer.10399
fatcat:xzwrfi5dtbfifonn7433dfvafa
Impact of Single Trap Random Telegraph Noise on Heterojunction TFET SRAM Stability
2014
IEEE Electron Device Letters
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For sub-0.2 V operation (Vcc), HTFET ST SRAM offers 15% improvement in read-write noise margins along with better variation immunity from RTN over Si-FinFET ST SRAM. ...
A comparison with iso-area 6T Si-FinFET SRAM with wider size transistors shows 43% improved read noise margin in 10T HTFET ST SRAM at Vcc = 0.175 V. ...
Intrinsic read/write noise margins of ST2 SRAM improve in HTFET design for sub-0.225 V, over subthreshold Si-FinFET. ...
doi:10.1109/led.2014.2300193
fatcat:5wecumajfvcvporuk334t2khti
Tunnel FET technology: A reliability perspective
2014
Microelectronics and reliability
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Given its unique device characteristics such as the asymmetrical source/drain design induced uni-directional conduction, enhanced on-state Miller capacitance effect and steep switching at low voltages, ...
Because TFET operates at low supply voltage range (V DD < 0:5 V) to outperform CMOS, reliability issues can have profound impact on the circuit design from the practical application perspective. ...
This work was supported in part by the Center for Low Energy Systems Technology (LEAST), one of the six SRC STARnet Centers, sponsored by MARCO and DARPA, and was also supported in part by the National ...
doi:10.1016/j.microrel.2014.02.002
fatcat:g4bvkvuhyjfplglxsa67qwn5da
Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications
2021
Electronics
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The data-dependent low-power 10T (D2LP10T) SRAM cell is used for the R-VDD scaled architecture with the improved stability and lower power consumption. ...
We analyze the failure probability during read, write, and hold mode, which shows that the proposed D2LP10T cell exhibits the lowest failure rate compared to other existing cells. ...
For that purpose, an error-tolerant energy-efficient data-dependent 10T SRAM cell is used with improved read, write, and hold stability even at lower supply voltage. ...
doi:10.3390/electronics10141718
fatcat:veoko7rnsfdepnapw7b3lcfkmm
Design and Analysis of Soft Error Rate in FET/CNTFET Based Radiation Hardened SRAM Cell
2021
Sensors
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Also, the robustness of the memory cell is tested against the variation in process, voltage and temperature. ...
Though CNTFET surges with high power consumption, it exhibits better noise margin and depleted access time. ...
Institutional Review Board Statement: Not applicable. Informed Consent Statement: Not applicable.
Data Availability Statement: The data can be available on the basis of request. ...
doi:10.3390/s22010033
pmid:35009576
pmcid:PMC8747695
fatcat:dxdcirbzu5e73isrkyvxby53vm
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