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Amnesic cache management for non-volatile memory

Dongwoo Kang, Seungjae Baek, Jongmoo Choi, Donghee Lee, Sam H. Noh, Onur Mutlu
2015 2015 31st Symposium on Mass Storage Systems and Technologies (MSST)  
One characteristic of non-volatile memory (NVM) is that, even though it supports non-volatility, its retention capability is limited.  ...  This retention relaxation can enhance the overall cache performance in terms of latency and energy since the data retention capability is proportional to the write latency.  ...  Myoungsoo Jung, and anonymous reviewers for their insightful comments.  ... 
doi:10.1109/msst.2015.7208291 dblp:conf/mss/KangBCLNM15 fatcat:n2kxwmmalffgncq6nr7mzbaxpe

Energy and Performance Analysis of STTRAM Caches for Mobile Applications [article]

Kyle Kuan, Tosiron Adegbija
2019 arXiv   pre-print
This paper studies the viability of STTRAM caches for mobile workloads from the perspective of energy and latency.  ...  Specifically, we explore the benefits of reduced retention STTRAM caches for mobile applications.  ...  The 10ms cache provided a balance between the overhead of expiration misses in the 1ms cache and the write latency of the 100ms cache.  ... 
arXiv:1908.04744v1 fatcat:cy7crvsaffd2pc3gc7v3lgxrze

Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design

Kyle Kuan, Tosiron Adegbija
2019 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
most important cache requirements that may vary for different applications.  ...  In the context of the increasingly popular Spin-Transfer Torque RAM (STT-RAM) cache, the retention time, which defines how long the cache can retain a cache block in the absence of power, is one of the  ...  Note that LARS requires minimal modifications to the cache controller, since these processes (e.g., writing back/invalidating a cache block) are implemented in state-of-the-art cache controllers.  ... 
doi:10.1109/tcad.2019.2912920 fatcat:n7abshzn5zgwfovoy6sxlgj62a

A Hybrid Disk-Aware Spin-Down Algorithm with I/O Subsystem Support

Timothy Bisson, Scott A. Brandt, Darrell D.E. Long
2007 Performance, Computing and Communications Conference (IPCCC), IEEE International  
Hybrid disks with a small amount of non-volatile flash memory (NVCache) are coming on the market.  ...  4) NVCache Write-Throttling.  ...  Figure 6 shows the results for a 256MB NVCache with write-caching, Artificial Idle Periods, and a Read-Miss Cache as a function of the maximum Read-Miss Cache size.  ... 
doi:10.1109/pccc.2007.358900 dblp:conf/ipccc/BissonBL07 fatcat:5ht5wkomyzgp5g4jyb23ckxgam

Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory

Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C.Hunter, Lizy K. John
2010 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture  
This paper shows how currently-employed methods to schedule refresh operations are ineffective in mitigating the significant performance degradation caused by longer refresh times.  ...  DRAM is ubiquitous as a main memory technology, but while DRAM's per-chip density and frequency continue to scale, the time required to refresh its dynamic cells has grown at an alarming rate.  ...  The authors acknowledge the use of the Archer infrastructure for their simulations.  ... 
doi:10.1109/micro.2010.22 dblp:conf/micro/StuecheliKHJ10 fatcat:ovzb6ogo4zfjnfr22uo3xjhnle

Mortar

Jinho Hwang, Ahsen Uppal, Timothy Wood, Howie Huang
2014 SIGPLAN notices  
This allows the hypervisor to control eviction policies and prioritize access to the cache.  ...  We present two uses for our Mortar framework: as a cache for prefetching disk blocks, and as an application-level distributed cache that follows the memcached protocol.  ...  Acknowledgments We thank the reviewers for their help improving this paper. This work was supported in part by NSF grants CNS-1253575, CNS-1350766, and OCI-0937875.  ... 
doi:10.1145/2674025.2576203 fatcat:e6j4vop7yjds3mpvrdzh3r74gm

Host managed contention avoidance storage solutions for Big Data

Pratik Mishra, Arun K. Somani
2017 Journal of Big Data  
This results in performance gain of 6-23% for MapReduce workloads when compared to BID-HDD and 33-54% over best performing Linux scheduling scheme.  ...  This results in performance gain of 6-23% for MapReduce workloads when compared to BID-HDD and 33-54% over best performing Linux scheduling scheme.  ...  , UK as "Bulk I/O Storage Management for Big Data Applications" [42] .  ... 
doi:10.1186/s40537-017-0080-9 fatcat:t2ni3rvbkvdapk2to7skgp445i

What is the future of disk drives, death or rebirth?

Yuhui Deng
2011 ACM Computing Surveys  
Finally, it discusses two of the important evolutions of the disk drives: hybrid disk and solid state disk.  ...  First of all, it briefly introduces the development of disk drives, and deconstructs disk performance and power consumption.  ...  The writing of this paper is inspired by his insightful comments in the community. In addition, I am grateful to Prof.  ... 
doi:10.1145/1922649.1922660 fatcat:zz3kcy54gfh4zj2oauq455ozxq

Client-Side Component Caching [chapter]

Christoph Pohl, Alexander Schill
2003 Lecture Notes in Computer Science  
Locality of referenced data is an important aspect for distributed computing. Caching is commonly employed to achieve this goal.  ...  An advanced mechanism for dynamic adaptation of the caching service to changing access characteristics is introduced in the second part.  ...  Divergence Caching [20] illuminates the aspects of static and dynamic caching, i.e. fixed and variable refresh rates.  ... 
doi:10.1007/978-3-540-40010-3_13 fatcat:mhaadvi6hbbwvoqft5h435nuia

A Survey on Tiering and Caching in High-Performance Storage Systems [article]

Morteza Hoseinzadeh
2019 arXiv   pre-print
To address this issue, a network of various types of storing media is used to deliver the high performance of expensive devices such as solid state drives and non-volatile memories, along with the high  ...  In software, caching and tiering are long-established concepts for handling file operations and moving data automatically within such a storage network and manage data backup in low-cost media.  ...  To the same end, Expiration-Time Driven (ETD) [10] cache algorithm delays a cache block eviction to its expiration time, and instead of updating the cache on a miss, it the evicts a block when it is  ... 
arXiv:1904.11560v1 fatcat:e752fsvuzbcxtmqjxg4ezlptku

Reducing DRAM Access Latency by Exploiting DRAM Leakage Characteristics and Common Access Patterns [article]

Hasan Hassan
2016 arXiv   pre-print
To exploit this observation, we propose to track the addresses of recently-accessed rows in a table in the memory controller.  ...  We evaluate ChargeCache on a wide variety of workloads and show that it provides significant performance and energy benefits for both single-core and multi-core systems.  ...  , 4MB cache size Memory Controller 64-entry read/write request queues, FR-FCFS scheduling policy [76, 99], open/closed row policy [39, 40] for single/multi core DRAM DDR3-1600 [56], 800MHz bus  ... 
arXiv:1609.07234v1 fatcat:5iuox7vjmndu3dciwbvlzpc5hu

Quantifying and improving I/O predictability in virtualized systems

Cheng Li, I. Goiri, A. Bhattacharjee, R. Bianchini, T. D. Nguyen
2013 2013 IEEE/ACM 21st International Symposium on Quality of Service (IWQoS)  
of both the SSD cache and the HDD.  ...  Vir-tualFence uses three main techniques: (1) non-work-conserving time-division I/O scheduling, (2) a small solid-state (SSD) cache in front of a much larger hard disk drive (HDD), and (3) spacepartitioning  ...  The scheduler informs a driver instance when its assigned slot is scheduled, at which time it is allowed to forward requests to the SSD and/or the HDD until the slot time expires.  ... 
doi:10.1109/iwqos.2013.6550269 dblp:conf/iwqos/LiGBBN13 fatcat:hd6lvh34mbaapmdbjskksxmpsq

An Efficient STT-RAM Last Level Cache Architecture for GPUs

Mohammad Hossein Samavatian, Hamed Abbasitabar, Mohammad Arjomand, Hamid Sarbazi-Azad
2014 Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14  
In this paper, having investigated the behavior of GPGPU applications, we present an efficient L2 cache architecture for GPUs based on STT-RAM technology.  ...  They have however two important issues, high energy and latency of write operations, that have to be addressed. Low data retention time STT-RAMs can reduce the energy and delay of write operations.  ...  For write efficiency, we use a simple buffering logic to take care of data expiration in LR cache and postpone refresh of data blocks to the last cycles of retention period.  ... 
doi:10.1145/2593069.2593086 dblp:conf/dac/SamavatianAAS14 fatcat:k5tdiszs5bbflgwgpnove4jj4i

An efficient STT-RAM last level cache architecture for GPUs

Mohammad Hossein Samavatian, Hamed Abbasitabar, Mohammad Arjomand, Hamid Sarbazi-Azad
2014 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)  
In this paper, having investigated the behavior of GPGPU applications, we present an efficient L2 cache architecture for GPUs based on STT-RAM technology.  ...  They have however two important issues, high energy and latency of write operations, that have to be addressed. Low data retention time STT-RAMs can reduce the energy and delay of write operations.  ...  For write efficiency, we use a simple buffering logic to take care of data expiration in LR cache and postpone refresh of data blocks to the last cycles of retention period.  ... 
doi:10.1109/dac.2014.6881524 fatcat:z7xdbgkyczb7zapa4ejojlfohi

A Survey of Architectural Techniques for Managing Process Variation

Sparsh Mittal
2016 ACM Computing Surveys  
In this paper, we present a survey of architectural techniques for managing process variation (PV) in modern processors.  ...  The aim of this paper is to provide insights to the researchers into the state-of-art in PV management techniques and motivate them to further improve these techniques for designing PV resilient processors  ...  The mem-0:20 ory controller inserts activate commands into command queues for future scheduling.  ... 
doi:10.1145/2871167 fatcat:6isx7an56ze63jqnpbkuw5pdcm
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