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RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays using Evolutionary Algorithms [article]

Niansong Zhang, Xiang Chen, Nachiket Kapre
2020 arXiv   pre-print
cost, and clock frequency when mapping FPGA hard block intensive designs such as systolic arrays on Xilinx UltraScale+ FPGAs.  ...  Instead, we formulate an automatic FPGA placement algorithm for these hard blocks as a multi-objective optimization problem that targets wirelength squared and maximum bounding box size metrics.  ...  We present an end-to-end hard block placement workflow for resource-intensive systolic array designs on modern heterogeneous FPGAs.  ... 
arXiv:2002.06998v3 fatcat:ygt7g7ziqvgnbi4dcnexgdpkpa

Table of Contents

2020 2020 30th International Conference on Field-Programmable Logic and Applications (FPL)  
of Guelph, Canada), Gary Grewal (University of Guelph, Canada), and Shawki Areibi (University of Guelph, Canada) RapidLayout: Fast Hard Block Placement of FPGA-Optimized Systolic Arrays using Evolutionary  ...  Algorithms 145 Niansong Zhang (Sun Yat-sen University, China), Xiang Chen (Sun Yat-sen University, China), and Nachiket Kapre (University of Waterloo, Canada) Timing-Driven Placement for FPGA Architectures  ... 
doi:10.1109/fpl50879.2020.00004 fatcat:ltbajx7zkvanjfbcxjirvu56ha