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Architecture and Implementation of a Reduced EPIC Processor

Jun GAO, Minxuan ZHANG, Zuocheng XING, Chaochao FENG
2013 IEICE transactions on information and systems  
to enhance Instruction-Level Parallelism (ILP).  ...  The die size of the REPICP is 100 mm 2 (10 × 10), and consumes only 12 W power when running at 300 MHz. key words: ILP, EPIC, IA-64, processor architecture, hardware implementation  ...  REPICP is a reduced design based on IA-64 architecture, which removes the IA-32 engine, reduces instruction dispatch, simplifies memory hierarchy from IA-64 threelevel to REPICP two-level, decreases memory  ... 
doi:10.1587/transinf.e96.d.9 fatcat:66x2fqheznbute67efkbz3sat4

Page 811 of Linguistics and Language Behavior Abstracts: LLBA Vol. 26, Issue 2 [page]

1992 Linguistics and Language Behavior Abstracts: LLBA  
(Coll Education National-Louis U, Evans- ton IL 60201), Vocabulary Instruction in Content Classes for Special Needs Learners: Why and How?  ...  It is conclud- ed that systematic instructional efforts could be vitally important for dys- lexics. 57 References. Adapted from the source document.  ... 

Trace-driven rapid pipeline architecture evaluation scheme for ASIP design

Jun Kyoung Kim, Tag Gon Kim
2003 Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC  
With latency information for every stage, we can decide if an instruction in one stage can proceed to the next stage or if an instruction can be issued for each cycle without evaluating the value for registers  ...  This paper proposes a rapid evaluation scheme of pipeline architecture using phase-accurate simulation with only delay model and trace.  ...  architecture. • R IA ⊆ IS × AM : A relation between the instruction set and addressing modes..  ... 
doi:10.1145/1119772.1119798 dblp:conf/aspdac/KimK03 fatcat:qlrxfbfddbdxrbiubtne5imeye

In-system FPGA prototyping of an itanium microarchitecture

Roland E. Wunderlich, James C. Hoe
2004 Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays - FPGA '04  
This is an effort toward developing a flexible microprocessor prototyping framework for rapid design exploration.  ...  The microarchitecture model includes details such as multi-bundle instruction fetch, decode and issue; parallel pipelined execution units with scoreboarding and predicated bypassing; and multiple levels  ...  We thank Bluespec Inc. for providing the Bluespec compiler and Intel Corporation for providing the FPGA platform.  ... 
doi:10.1145/968280.968346 dblp:conf/fpga/WunderlichH04 fatcat:yfuzc4apongoxdqgqzn4jupafm

An Overview of Dyslexia: Definition, Characteristics, Assessment, Identification, and Intervention

Jane Roitsch, Silvana Watson
2019 Science Journal of Education  
Dyslexia assessments can guide professions in ways to best administer treatment, such as via strategies to enhance word training and improve decoding skills.  ...  Objective: The purpose of this article is to provide an overview of dyslexia, its characteristics, assessment and identification, and intervention techniques for the condition.  ...  Process Assessment of the Learner, Second Edition: Diagnostics for Reading and Writing (PAL-II Reading and Writing). 5. RAN/RAS: Rapid Automatized Naming and Rapid Alternating Stimulus Tests. 6.  ... 
doi:10.11648/j.sjedu.20190704.11 fatcat:5dmt32g37rhbnp3vvo5owr73pi

Shellcode_IA32: A Dataset for Automatic Shellcode Generation [article]

Pietro Liguori, Erfan Al-Hossami, Domenico Cotroneo, Roberto Natella, Bojan Cukic, Samira Shaikh
2021 arXiv   pre-print
We assemble and release a novel dataset (Shellcode_IA32), consisting of challenging but common assembly instructions with their natural language descriptions.  ...  This dataset consists of 3,200 examples of instructions in assembly language for IA-32 (the 32-bit version of the x86 Intel Architecture) from publicly-available security exploits.  ...  We enriched the dataset by adding examples of assembly programs for the IA-32 architecture from popular tutorials and books (Duntemann, 2011; Kusswurm, 2014; Tutorialspoint, Accessed: 2021-04-22) to  ... 
arXiv:2104.13100v3 fatcat:thhla6bcjzfjhoxuwadd36th3u

Performance Enhancement Of Motion Estimation Using Sse2 Technology

Trung Hieu Tran, Hyo-Moon Cho, Sang-Bock Cho
2008 Zenodo  
Therefore, the timing constraints for running these motion estimation algorithms not only challenge for the video codec but also overwhelm for some of processors.  ...  However, these studies are for fast search algorithms themselves while almost image and video compressions are operated with software based.  ...  Streaming SIMD Extensions (SSE) from the Intel Pentium III marked the advent of 70 new instructions to the IA-32 ISA.  ... 
doi:10.5281/zenodo.1327908 fatcat:4s7xheqeszdj7hgzicft64iaeu

A thermal-aware on-line fault tolerance method for TSV lifetime reliability in 3D-NoC systems

Khanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran
2020 IEEE Access  
For the other works (IaS and TSV-OCT), we could observe the rapid increase of WCET. Table 4 shows the hardware complexity of the router design.  ...  The controller block gives instructions for switching between group/redundant TSVs and synchronization.  ... 
doi:10.1109/access.2020.3022904 fatcat:giopjrulsjew7gzuhiyyypu5he

Curriculum-Based Measurement of Oral Reading Fluency: A Confirmatory Analysis of its Relation to Reading

Mark R. Shinn, Nancy Knutson, Roland H. Good, W. David Tilly, Vicki L. Collins
1992 School psychology review  
Is Fluency Just Rapid Decoding?  ...  For example, Car- nine and Silbert (1979), proponents of a behaviorally based direct instruction approach, also identify rapid decoding as a fundamental skill in reading com- prehension.  ... 
doi:10.1080/02796015.1992.12085629 fatcat:pzjhd5dgqzdaflljekrrgxby3a

The microprocessor today

M. Slater
1996 IEEE Micro  
TLB (32 entries) Branch target buffer Instruction fetch unit Data TLB (64 entries) In-order section Simple decoder Simple decoder General decoder Micro-op sequencer Reorder buffer  ...  Cache access and instruction decoding are each split across two and one-half clock cycles.  ...  This ensures the microprocessor's role at the heart of the electronics industry for the next 25 years or longer.  ... 
doi:10.1109/mm.1996.546563 fatcat:2crlavzi3fhh3otclfte3nprpu

Cue to action processing in motor cortex populations

Naveen G. Rao, John P. Donoghue
2014 Journal of Neurophysiology  
Population decoding revealed that MI's coding of cue direction evolved temporally, likely going from cue to action generation.  ...  These findings support a view that MI is an integral part of a cue-to-action network for immediate responses to environmental stimuli.  ...  The C1 cue instructed the same direction as the subsequent C2 cue, except C1 did not instruct immediate movement.  ... 
doi:10.1152/jn.00274.2013 pmid:24174650 pmcid:PMC3921381 fatcat:hwwn6rchjvhzpay6qz6zzqxeya

Reading comprehension and reading related abilities in adolescents with reading disabilities and attention-deficit/hyperactivity disorder

Karen Ghelani, Robindra Sidhu, Umesh Jain, Rosemary Tannock
2004 Dyslexia  
basis for instruction of text comprehension.  ...  decoded orally.  ... 
doi:10.1002/dys.285 pmid:15573965 fatcat:x2thdcl5unexfmuu22y4xzbx3y

A description of the verbal behavior of students during two reading instruction methods

Patricia M. Daly
1987 The Analysis of Verbal Behavior  
A description of student responding was generated for these methods.  ...  It is suggested that students who can generate strong intraverbal responses and who may have visual discrimination problems during early reading instruction may benefit from use of the language experience  ...  STUDENT A 40 Story 1 Story 2 00 g 364 9 _ Textual-intraverbals 100 mm 32- A Textuals 80 0F m Z 28- A iA Intraverbals 70 Z 2O 24 t-% Story read non-echoically 6 50°0 1  ... 
doi:10.1007/bf03392821 pmid:22477535 pmcid:PMC2748451 fatcat:l2nr6trm5fhphdkkclcfjgscra

Binary compatibility for embedded systems using greedy subgraph mapping

XuHao Chen, Li Shen, ZhiYing Wang, Zhong Zheng, Wei Chen
2014 Science China Information Sciences  
Moreover, GSM causes slightly extra overhead and negligible slowdown of translation and enables 10% performance improvement for target code execution.  ...  Experimental results demonstrate that GSM generates higher quality target code than a conventional implementation, which brings an average code expansion rate close to 1.3 for the selected 11 benchmarks  ...  Intel IA-32 EL [15] translates IA-32 instructions into Itanium instructions to provide the ability to execute IA-32 applications on Intel Itanium processor.  ... 
doi:10.1007/s11432-014-5089-5 fatcat:5vdj2n63lralldojivedjp3nrm

A software high performance APL interpreter

Harry J. Saal, Zvi Weiss
1979 ACM SIGAPL APL Quote Quad  
(For example, on 370 each field is a 32 bit word for convenience; in a microprogrammed environment one would ~ack fields much better than that.) 3 Generally virtual machine instructions are N+l  ...  Thus rather than providing for rapid error traceback, or accoModation to other rare events, we take the position that execution should be as rapid as possible, leaving just enough of a trail to "pick up  ... 
doi:10.1145/390009.804441 fatcat:cg6qfxc2qnd7lgbnm65hrsklle
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