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Random verification Strategy for Microcontroller based Subsystems for faster Convergence

Ruchita Pathak, Vishal Dewan, Aravind Bhat
2019 EAI Endorsed Transactions on Cloud Systems  
There is no standard approach for developing random verification environment for such subsystems, thus resulting in increased time for development and maintenance.  ...  A typical microcontroller-based system often includes multiple interfaces with an ability to support clock gating and other low power features.  ...  The authors would like to acknowledge Mangesh Kondalkar for his valuable contributions towards development of this Methodology and implementation.  ... 
doi:10.4108/eai.16-7-2019.162214 fatcat:zxdrksweg5gghdsz3z4lcpyxoi

Hardware-In-The-Loop and Software-In-The-Loop Testing of the MOVE-II CubeSat

Jonis Kiesbye, David Messmann, Maximilian Preisinger, Gonzalo Reina, Daniel Nagy, Florian Schummer, Martin Mostad, Tejas Kale, Martin Langer
2019 Aerospace (Basel)  
This article reports the ongoing work on an environment for hardware-in-the-loop (HIL) and software-in-the-loop (SIL) tests of CubeSats and the benefits gained from using such an environment for low-cost  ...  The presented results include the verification of MOVE-II's attitude determination and control algorithms, the verification of the power budget, and the training of the operator team with realistic simulated  ...  It is obvious that, on average, the extended LQR controller converges faster than the spinning sun-pointing controller.  ... 
doi:10.3390/aerospace6120130 fatcat:qgkxnr56ffbyfougsuh6ebeylm

Numerical Method for Power Losses Minimization of Vector-Controlled Induction Motor

Alex Borisevich
2015 International Journal of Power Electronics and Drive Systems  
Adjustment rule for control variable is proposed which speeds-up the method convergence in comparison with linear variation of input.  ...  Finally a new continuous-time search algorithm for solving the problem of minimizing power consumption was given.  ...  Gernot Schullerus from the Reutlingen University, especially for discussions on problem formulation and the method itself.  ... 
doi:10.11591/ijpeds.v6.i3.pp486-497 fatcat:j6con5hp5rfbjf6czj5lkmd6my

Integration and Verification Approach of ISTSat-1 CubeSat

João P. Monteiro, Rui M. Rocha, Alexandre Silva, Rúben Afonso, Nuno Ramos
2019 Aerospace (Basel)  
radiation (EMC) testing on all subsystems.  ...  approach to spacecraft development in favor of a more iterative approach, allowing for the system-level verification of unfinished prototypes.  ...  The team's software development strategy relies on a CI process that automates testing and verification.  ... 
doi:10.3390/aerospace6120131 fatcat:3ncs4hy67rerhjdgrp5s7ik7qy

Practical Sender Authentication Scheme for In-vehicle CAN with Efficient Key Management

Taek-Young Youn, Yousik Lee, Samuel Woo
2020 IEEE Access  
To evaluate the performance and security of the proposed scheme, we conduct hardware and network simulator based evaluation.  ...  For more information, see https://creativecommons.org/licenses/by/4.0/ VOLUME 8, 2020  ...  EVALUATION To measure the time taken for the PreAuthCode generation and verification and session key generation, we performed a hardware-based performance evaluation.  ... 
doi:10.1109/access.2020.2992112 fatcat:72v6ovgz2jdlxm5qtilfdchvfy

An MPPT Control of a PMSG-Based WECS with Disturbance Compensation and Wind Speed Estimation

Janusz Baran, Andrzej Jąderko
2020 Energies  
The presented control algorithm is based on feedforward compensation of the wind turbine aerodynamic torque estimated using a linear disturbance observer (DOB).  ...  The torque estimate is employed to determine the effective wind speed, required for setting the reference angular speed, using numerical zero search of a nonlinear function.  ...  Acknowledgments: The authors would like to acknowledge the MMB Drives Sp. z o.o. company, Gdańsk, Poland, for making available experimental data.  ... 
doi:10.3390/en13236344 fatcat:pn7kz76gsfhzxkgr5snfhezopm

Hardware-software codesign of embedded systems

M. Chiodo, P. Giusto, A. Jurecska, H.C. Hsieh, A. Sangiovanni-Vincentelli, L. Lavagno
1994 IEEE Micro  
We describe analysis techniques for hardware and software relevant to the architectural choices required for hardware-software co-design.  ...  We also describe design and synthesis techniques for co-design and related problems. tor WIL's.  ...  Srivastava et al. used templates to design real-time subsystems for a workstation-based embedded architecture [93] , [94] .  ... 
doi:10.1109/40.296155 fatcat:ry7g2gcfkvdo3fnmi73knppf5a

Hardware-software co-design of embedded systems

W.H. Wolf
1994 Proceedings of the IEEE  
We describe analysis techniques for hardware and software relevant to the architectural choices required for hardware-software co-design.  ...  We also describe design and synthesis techniques for co-design and related problems. tor WIL's.  ...  Srivastava et al. used templates to design real-time subsystems for a workstation-based embedded architecture [93] , [94] .  ... 
doi:10.1109/5.293155 fatcat:jytgx6etfnhbpfz5zqxbv6oiua

Proof-of-PUF Enabled Blockchain: Concurrent Data and Device Security for Internet-of-Energy

Rameez Asif, Kinan Ghanem, James Irvine
2020 Sensors  
It stipulates an emerging concept of Blockchain that integrates hardware security primitives via PUFs to solve bandwidth, integration, scalability, latency, and energy requirements for the Internet-of-Energy  ...  Acknowledgments: The authors would like to thank Hannah Rudman (Strategic Transformation Director) at Wallet Services, Edinburgh, UK for providing in-depth knowledge on Distributed Ledger Technology (DLT  ...  Initial findings [177] on PUF-based authentication showed 1000x faster processing times than well-established PoW and 5x faster than previously recorded hardware-based solutions.  ... 
doi:10.3390/s21010028 pmid:33374599 pmcid:PMC7793093 fatcat:h2b4djvqojdehjxrku4nkjl2dq

Energy Efficient Computing Systems: Architectures, Abstractions and Modeling to Techniques and Standards [article]

Rajeev Muralidhar and Renata Borovica-Gajic and Rajkumar Buyya
2020 arXiv   pre-print
(hardware or software or both) so as to be able to perform what-if analysis, (c) techniques used for implementing energy efficiency at different levels of the stack, (d) verification techniques used to  ...  We have now entered the era of domain-specific architectures for new workloads like AI and ML.  ...  Targeted verification of each IP block, including CPU cores, GPUs, memory, and others can be done using traditional silicon verification techniques through a combination of random, targeted and functional  ... 
arXiv:2007.09976v2 fatcat:enrfj2qgerhyteapwykxcb5pni

Arizona State University Satellite 1 (ASUSat1): Low-Cost, Student-Designed Nanosatellite

Assi Friedman, Brian Underhill, Shea Ferring, Christian Lenz, Joel Rademacher, Helen Reed
2002 Journal of Spacecraft and Rockets  
Both cameras were to work as inde- pendent units with each having | MB of random access memory for image storage and a microcontroller unit for image capture and compression.  ...  The central processing unit had a 1-MB random access mem- ory bank, which was the microcontroller unit’s full capacity.  ... 
doi:10.2514/2.3873 fatcat:b2fjgilfgbeeze2n2f5yjrizpm

Smart Measuring Instruments for Cyber-Physical Systems

Mykola Mykyychuk, Svyatoslav Yatsyshyn, Bohdan Stadnyk, Yaroslav Lutsyk
2016 Advances in Cyber-Physical Systems  
Verification of the metrological subsystems for parameters determining the controlled equipment and processes through the development, implementation and realization of specific metrology and standardization  ...  As result, it spares the time necessary for adaptation strategy that has to be fulfilled.  ...  INTRODUCTION Smart measuring instruments (further -MIs) are the prerequisite for CPS design as they constitute the essential units of information and measurement subsystems.  ... 
doi:10.23939/acps2016.01.007 fatcat:p37dllrntrannfjhbunnhr6r2i

Design of embedded systems: formal models, validation, and synthesis

S. Edwards, L. Lavagno, E.A. Lee, A. Sangiovanni-Vincentelli
1997 Proceedings of the IEEE  
The concurrent design process for such embedded systems involves solving the specification, validation, and synthesis problems.  ...  Such systems are often heterogeneous in implementation technologies and design styles, for example by combining hardware ASICs with embedded software.  ...  We also thank Harry Hsieh for his help with a first draft of this work.  ... 
doi:10.1109/5.558710 fatcat:4v34mhx7hjf5zjt4aap356zvb4

Design of Embedded Systems: Formal Models, Validation, and Synthesis [chapter]

Stephen Edwards, Luciano Lavagno, Edward A. Lee, Alberto Sangiovanni-Vincentelli
2002 Readings in Hardware/Software Co-Design  
The concurrent design process for such embedded systems involves solving the specification, validation, and synthesis problems.  ...  Such systems are often heterogeneous in implementation technologies and design styles, for example by combining hardware ASICs with embedded software.  ...  We also thank Harry Hsieh for his help with a first draft of this work.  ... 
doi:10.1016/b978-155860702-6/50009-0 fatcat:um7k7am5ergnrcizrrkbmzoz7a

Random Error Reduction Algorithms for MEMS Inertial Sensor Accuracy Improvement—A Review

Shipeng Han, Zhen Meng, Olatunji Omisore, Toluwanimi Akinyemi, Yuepeng Yan
2020 Micromachines  
Thus, random error processing is essential for proper elimination of artifact signals and improvement of the accuracy and reliability from such sensors.  ...  underlying systems, and other random noise.  ...  Acknowledgments: The authors would like to gratefully acknowledge the support from Smart Sensing Center, Institute of Microelectronics, Chinese Academy of Sciences for working platform.  ... 
doi:10.3390/mi11111021 pmid:33233457 fatcat:b7oc7duoxjd7rgzafeggdfh7ka
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