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Robust Compact Model for Bipolar Oxide-Based Resistive Switching Memories

Marc Bocquet, Damien Deleruyelle, Hassen Aziza, Christophe Muller, Jean-Michel Portal, Thomas Cabout, Eric Jalaguier
2014 IEEE Transactions on Electron Devices  
In this paper, we propose a physics-based compact model used in electrical simulator for bipolar OxRAM memories.  ...  To fully explore new design concepts such as distributed memory in logic or biomimetic architectures, robust OxRAM compact models must be developed and implemented into electrical simulators to assess  ...  Hence, a robust OxRAM compact model is required to assess and validate new concepts before fabrication.  ... 
doi:10.1109/ted.2013.2296793 fatcat:lg2agr5a5nabfc2etakbahw6ri

Linear Time and Memory-Efficient Computation

Kenneth W. Regan
1996 SIAM journal on computing (Print)  
A realistic model of computation called the Block Move (BM) model is developed.  ...  The BM regards computation as a sequence of finite transductions in memory, and operations are timed according to a memory cost parameter µ.  ...  We find it useful to regard GSTs as "states" in a BM machine diagram, reading the machine in terms of the specific functions they perform, and submerging the individual states of the GSTs onto a lower  ... 
doi:10.1137/s0097539793251888 fatcat:glwba3jtvzdc5b2uig3zg3sh2y

Improved external memory BFS implementations [chapter]

Deepak Ajwani, Ulrich Meyer, Vitaly Osipov
2007 2007 Proceedings of the Ninth Workshop on Algorithm Engineering and Experiments (ALENEX)  
BFS is well-understood in the RAM model. There exists a simple linear time algorithm [15] (hereafter refered as IM BFS) for the BFS traversal in a graph.  ...  Ajwani et al. [3] showed that the randomized variant of the o(n) I/O algorithm of Mehlhorn and Meyer [24] (MM BFS) can compute the BFS level decomposition for large graphs (around a billion edges) in a  ...  The authors also acknowledge the usage of the computing resources of the University of Karlsruhe.  ... 
doi:10.1137/1.9781611972870.1 dblp:conf/alenex/AjwaniMO07 fatcat:kygucguaqbevpk2t7ifggu4gpm

Neuromorphic computing using non-volatile memory

Geoffrey W. Burr, Robert M. Shelby, Abu Sebastian, Sangbum Kim, Seyoung Kim, Severin Sidler, Kumar Virwani, Masatoshi Ishii, Pritish Narayanan, Alessandro Fumarola, Lucas L. Sanches, Irem Boybat (+5 others)
2016 Advances in Physics: X  
We then survey recent research in which different types of NVM devices -including phase change memory, conductive-bridging RAM, filamentary and nonfilamentary RRAM, and other NVMs -have been proposed,  ...  Dense crossbar arrays of non-volatile memory (NVM) devices represent one possible path for implementing massively-parallel and highly energy-efficient neuromorphic computing systems.  ...  Chen, Wilfried Haensch, Heike Riel and Dario Gil.  ... 
doi:10.1080/23746149.2016.1259585 fatcat:ff4l2l74jjdgjezjzw3rkniose

Compact Modeling Solutions for Oxide-Based Resistive Switching Memories (OxRAM)

Marc Bocquet, Hassen Aziza, Weisheng Zhao, Yue Zhang, Santhosh Onkaraiah, Christophe Muller, Marina Reyboz, Damien Deleruyelle, Fabien Clermidy, Jean-Michel Portal
2014 Journal of Low Power Electronics and Applications  
To fully explore new design concepts such as distributed memory in logic, OxRAM compact models have to be developed and implemented into electrical simulators to assess performances at a circuit level.  ...  In this paper, we present compact models of the bipolar OxRAM memory based on physical phenomenons. This model was implemented in electrical simulators for single device up to circuit level. J.  ...  Acknowledgements This work was supported in part by the ANR project DIPMEM (Design and Demonstration of Digital IP based on Emerging Non-Volatile MEMories) under grant ANR-12-NANO-0010-04.  ... 
doi:10.3390/jlpea4010001 fatcat:q6ie4ksopnhojpfhmzrqtmzdoa

Memory and Information Processing in Neuromorphic Systems

Giacomo Indiveri, Shih-Chii Liu
2015 Proceedings of the IEEE  
more biological-like models of neurons and synapses together with a suite of adaptation and learning mechanisms analogous to the ones found in biological nervous systems.  ...  In this paper we present a survey of brain-inspired processor architectures that support models of cortical networks and deep neural networks.  ...  a wide range of robust signal processing and computing functions [134] .  ... 
doi:10.1109/jproc.2015.2444094 fatcat:enmuv4qr6bdktlh7t3rfwfj27i

Testing embedded memories in telecommunication systems

S. Barbagallo, M. Lobetti Bodoni, A. Benso, S. Chiusano, P. Prinetto
1999 IEEE Communications Magazine  
Moreover, strict reliability constraints usually impose very low fault latencies and a high degree of fault detection for both permanent and transient faults.  ...  This article analyzes major problems related to testing complex telecommunication systems, with particular emphasis on their memory modules, often so critical from the reliability point of view.  ...  In the actual implementation, the command memory is a 4000 x 16 bits dual-port static RAM, and the speech memory is a dual-port static RAM too, composed of six blocks of 1000 x 8 bits each.  ... 
doi:10.1109/35.769279 fatcat:5ruaizf4kjhgfj2dkhaoyjxfcq

TCAM Network Memory Error Detection and Correction Method

Thirumala Vidya Sagar S, B.D.Venkatramana Reddy
2022 International Journal of Engineering Technology and Management Sciences  
In particular, it is shown that by exploiting the fact that only a subset of the possible memory contents are valid, most single-bit errors can be corrected when the memories are protected with a parity  ...  The memories can be protected with a parity check to detect errors or with an error correction code to correct them, but this requires additional memory bits per word.  ...  The proposed solution addresses RAM memory with TCAM content, and each RAM word corresponds to a specific TCAM data pattern.  ... 
doi:10.46647/ijetms.2022.v06i03.019 fatcat:hpe3ygsh2bh3zn4maqdylfnmji

Neural associative memories and sparse coding

Günther Palm
2013 Neural Networks  
The importance of sparse coding of associative memory patterns is pointed out. The use of associative memory networks for large scale brain modeling is also mentioned.  ...  The theoretical, practical and technical development of neural associative memories during the last 40 years is described.  ...  Acknowledgments I would like to thank Miriam Schmidt and Martin Schels for helping me with the final preparation of the manuscript.  ... 
doi:10.1016/j.neunet.2012.08.013 pmid:23043727 fatcat:etgorhaq2nfodokplfi7p2s7ke

Cascaded Parallel Filtering for Memory-Efficient Image-Based Localization [article]

Wentao Cheng, Weisi Lin, Kan Chen, Xinfeng Zhang
2019 arXiv   pre-print
The camera pose can be computed from 2D-3D matches between a query image and Structure-from-Motion (SfM) models.  ...  Despite recent advances in IBL, it remains difficult to simultaneously resolve the memory consumption and match ambiguity problems of large SfM models.  ...  Acknowledgements: This research was supported by Singapore Ministry of Education Tier-2 Fund MOE2016-T2-2-057(S) and the National Research Foundation, Prime Minister's Office, Singapore under its International  ... 
arXiv:1908.06141v1 fatcat:3aguwbmhknbxxdbufex63skjny

In-Memory Nearest Neighbor Search with FeFET Multi-Bit Content-Addressable Memories [article]

Arman Kazemi, Mohammad Mehdi Sharifi, Ann Franchesca Laguna, Franz Müller, Ramin Rajaei, Ricardo Olivo, Thomas Kämpfe, Michael Niemier, X. Sharon Hu
2020 arXiv   pre-print
This paper proposes a novel distance function that can be natively evaluated with multi-bit content-addressable memories (MCAMs) based on ferroelectric FETs (FeFETs) to perform a single-step, in-memory  ...  Furthermore, this work experimentally demonstrates a 2-bit implementation of FeFET MCAM using AND arrays from GLOBALFOUNDRIES to further validate proof of concept.  ...  ACKNOWLEDGMENT This work was supported in part by ASCENT, one of six centers in JUMP, a SRC program sponsored by DARPA.  ... 
arXiv:2011.07095v1 fatcat:hpktzzvzine6hneimcolestkdi

The Price of Resiliency: a Case Study on Sorting with Memory Faults

Umberto Ferraro-Petrillo, Irene Finocchi, Giuseppe F. Italiano
2009 Algorithmica  
Another contribution of our computational study is a carefully engineered implementation of a resilient sorting algorithm, which appears robust to different memory fault patterns.  ...  We address the problem of sorting in the presence of faults that may arbitrarily corrupt memory locations, and investigate the impact of memory faults both on the correctness and on the running times of  ...  Acknowledgments We thank the anonymous referees for the many useful comments that improved the presentation of this paper.  ... 
doi:10.1007/s00453-008-9264-1 fatcat:6lttnu3hozhvnohng6n7wxcl4a

The Price of Resiliency: A Case Study on Sorting with Memory Faults [chapter]

Umberto Ferraro-Petrillo, Irene Finocchi, Giuseppe F. Italiano
2006 Lecture Notes in Computer Science  
Another contribution of our computational study is a carefully engineered implementation of a resilient sorting algorithm, which appears robust to different memory fault patterns.  ...  We address the problem of sorting in the presence of faults that may arbitrarily corrupt memory locations, and investigate the impact of memory faults both on the correctness and on the running times of  ...  Acknowledgments We thank the anonymous referees for the many useful comments that improved the presentation of this paper.  ... 
doi:10.1007/11841036_68 fatcat:yq2azlzvi5ht7mi3l62of5rinu

A Classification of Memory-Centric Computing

Hoang Anh Du Nguyen, Jintao Yu, Muath Abu Lebdeh, Mottaqiallah Taouil, Said Hamdioui, Francky Catthoor
2020 ACM Journal on Emerging Technologies in Computing Systems  
With these distinct metrics, the classification covers all computing architectures in general and memory-centric computing in specific.  ...  This paper presents a comprehensive classification of memory-centric computing, and discusses both conventional and emerging computing architectures.  ...  in a more compact architecture as compared with other architectures which make use of two devices per cell (i.e., Complementary Resistive 4Fig. 7 . 7 COMPUTATION-IN-MEMORY -PERIPHERY (CIM-P)The CIM-P  ... 
doi:10.1145/3365837 fatcat:n5cipv6h5vheppoa6krd5qmv7i

Stopless

Filip Pizlo, Daniel Frampton, Erez Petrank, Bjarne Steensgaard
2007 Proceedings of the 6th international symposium on Memory management - ISMM '07  
It was implemented on top of the Bartok compiler and runtime for C# and measurements demonstrate high responsiveness (a factor of a 100 better than previously published systems), virtually no pause times  ...  STOPLESS is the first collector that provides real-time responsiveness while preserving lock-freedom, supporting atomic operations, controlling fragmentation by compaction, and supporting modern parallel  ...  Acknowledgments We thank David Tarditi, Tim Harris, and the anonymous reviewers for many helpful remarks that greatly improved this presentation.  ... 
doi:10.1145/1296907.1296927 dblp:conf/iwmm/PizloFPS07 fatcat:ikxwtq2asfgstblrd2e4u5h33i
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