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RAIDR: Retention-aware intelligent DRAM refresh

Jamie Liu, Ben Jaiyen, Richard Veras, Onur Mutlu
2012 2012 39th Annual International Symposium on Computer Architecture (ISCA)  
In this paper, we propose RAIDR (Retention-Aware Intelligent DRAM Refresh), a low-cost mechanism that can identify and skip unnecessary refreshes using knowledge of cell retention times.  ...  Our key idea is to group DRAM rows into retention time bins and apply a different refresh rate to each bin.  ...  To this end, we propose Retention-Aware Intelligent DRAM Refresh (RAIDR). RAIDR groups DRAM rows into retention time bins based on the refresh rate they require to retain data.  ... 
doi:10.1109/isca.2012.6237001 dblp:conf/isca/LiuJVM12 fatcat:gizsbubpona57kuuksgkjme3ny

RAIDR

Jamie Liu, Ben Jaiyen, Richard Veras, Onur Mutlu
2012 SIGARCH Computer Architecture News  
In this paper, we propose RAIDR (Retention-Aware Intelligent DRAM Refresh), a low-cost mechanism that can identify and skip unnecessary refreshes using knowledge of cell retention times.  ...  Our key idea is to group DRAM rows into retention time bins and apply a different refresh rate to each bin.  ...  To this end, we propose Retention-Aware Intelligent DRAM Refresh (RAIDR). RAIDR groups DRAM rows into retention time bins based on the refresh rate they require to retain data.  ... 
doi:10.1145/2366231.2337161 fatcat:254j7q3mufaldpbtqv4znkihhi

RAIDR: Retention-Aware Intelligent DRAM Refresh

Jamie Liu, Ben Jaiyen, Richard Veras, Onur Mutlu
2018
In this paper, we proposeRAIDR (Retention-Aware Intelligent DRAM Refresh), a low-cost mechanism that can identify and skip unnecessary refreshes using knowledge of cell retention times.  ...  Our key idea is to group DRAM rows into retention time bins and apply a different refresh rate to each bin.  ...  To this end, we propose Retention-Aware Intelligent DRAM Refresh (RAIDR). RAIDR groups DRAM rows into retention time bins based on the refresh rate they require to retain data.  ... 
doi:10.1184/r1/6469205.v1 fatcat:7v32nck4g5dwvj4erklds6doja

DTail

Zehan Cui, Sally A. McKee, Zhongbin Zha, Yungang Bao, Mingyu Chen
2014 Proceedings of the 28th ACM international conference on Supercomputing - ICS '14  
DRAM cells must be refreshed (or rewritten) periodically to maintain data integrity, and as DRAM density grows, so does the refresh time and energy.  ...  Completely tracking multiple types of refresh information (e.g., row retention time and data validity) maximizes refresh reduction and lets us choose the most effective refresh schemes.  ...  [29] and the Retention-Aware Intelligent DRAM Refresh (RAIDR) of Liu et al. [20] . VRA stores each row's expected refresh period in registers inside the DRAM.  ... 
doi:10.1145/2597652.2597663 dblp:conf/ics/CuiMZBC14 fatcat:pes5z3uh3rghfcqfu543mh4jqa

Rethinking memory system design for data-intensive computing

Onur Mutlu
2015 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)  
dynamic/idle power reduction ~9% performance improvement  Benefits increase with DRAM capacity 30 Liu et al., "RAIDR: Retention-Aware Intelligent DRAM Refresh," ISCA 2012.  ...   Summary 24 Tolerating DRAM: Example Techniques  Retention-Aware DRAM Refresh: Reducing Refresh Impact  Refresh Access Parallelization: Reducing Refresh Impact  Tiered-Latency DRAM: Reducing  ... 
doi:10.1109/samos.2015.7363650 dblp:conf/samos/Mutlu15 fatcat:fc5a6u4sinhotaibqt6bsull2a

Flexible auto-refresh

Ishwar Bhati, Zeshan Chishti, Shih-Lien Lu, Bruce Jacob
2015 Proceedings of the 42nd Annual International Symposium on Computer Architecture - ISCA '15  
For example, prior works exploit the fact that a subset of DRAM rows can be refreshed at a slower rate than other rows due to access rate or retention period variations.  ...  The internal implementation of auto-refresh is completely opaque outside the DRAM-all the memory controller can do is to instruct the DRAM to refresh itselfthe DRAM handles all else, in particular determining  ...  Since most DRAM cells have high retention periods, prior retention aware techniques exploit row-granularity refreshing to reduce a large number of unnecessary refreshes [1] , [6] .  ... 
doi:10.1145/2749469.2750408 dblp:conf/isca/BhatiCLJ15 fatcat:4fy7jmmcnffwphnn4yszpbuiaa

Flexible auto-refresh

Ishwar Bhati, Zeshan Chishti, Shih-Lien Lu, Bruce Jacob
2015 SIGARCH Computer Architecture News  
For example, prior works exploit the fact that a subset of DRAM rows can be refreshed at a slower rate than other rows due to access rate or retention period variations.  ...  The internal implementation of auto-refresh is completely opaque outside the DRAM-all the memory controller can do is to instruct the DRAM to refresh itselfthe DRAM handles all else, in particular determining  ...  Since most DRAM cells have high retention periods, prior retention aware techniques exploit row-granularity refreshing to reduce a large number of unnecessary refreshes [1] , [6] .  ... 
doi:10.1145/2872887.2750408 fatcat:6sax4oe3ljcfhijy3lcqdliyhy

Memory scaling: A systems architecture perspective

Onur Mutlu
2013 2013 5th IEEE International Memory Workshop  
Specifically, we survey three key solution directions: 1) enabling new DRAM architectures, functions, interfaces, and better integration of the DRAM and the rest of the system, 2) designing a memory system  ...  At the same time, DRAM technology is experiencing difficult technology scaling challenges that make the maintenance and enhancement of its capacity, energy-efficiency, and reliability significantly more  ...  Retention-Aware Intelligent DRAM Refresh (RAIDR) [44] exploits this observation: it groups DRAM rows into bins (implemented as Bloom filters to minimize hardware overhead) based on the retention time  ... 
doi:10.1109/imw.2013.6582088 fatcat:z4sqlrylffa3velrmkgdv7ip3y

Main Memory Scaling: Challenges and Solution Directions [chapter]

Onur Mutlu
2015 More than Moore Technologies for Next Generation Computer Design  
predictable performance and QoS to applications sharing the memory system (i.e., QoS-aware memory systems).  ...  Specifically, we describe three major solution directions: 1) enabling new DRAM architectures, functions, interfaces, and better integration of the DRAM and the rest of the system (an approach we call  ...  Section 6.8 of this article is a condensed and slightly revised version of the introduction of an invited article that appeared in a special issue of the Intel Technology Journal, titled Error Analysis and Retention-Aware  ... 
doi:10.1007/978-1-4939-2163-8_6 fatcat:okw4kxakuja43kac65zy5c35ye

Research Problems and Opportunities in Memory Systems

2014 Supercomputing Frontiers and Innovations  
memory systems), 3) providing predictable performance and QoS to applications sharing the memory system (i.e., QoS-aware memory systems).  ...  Specifically, we describe three major new research challenges and solution directions: 1) enabling new DRAM architectures, functions, interfaces, and better integration of the DRAM and the rest of the  ...  Retention-Aware Intelligent DRAM Refresh (RAIDR) [114] exploits this observation: it groups DRAM rows into bins (implemented as Bloom filters [16] to minimize hardware overhead) based on the retention  ... 
doi:10.14529/jsfi140302 fatcat:2zfa7zk3qjgohdsgxmkkqaamuu

The Colored Refresh Server for DRAM

Xing Pan, Frank Mueller
2019 2019 IEEE 22nd International Symposium on Real-Time Distributed Computing (ISORC)  
Yet, access latencies to Dynamic Random Access Memory (DRAM) vary significantly due to DRAM refresh, which blocks access to memory cells. Variations further increase as DRAM density grows.  ...  By executing tasks in phase with periodic DRAM refreshes with opposing colors, memory requests no longer suffer from refresh interference.  ...  [4] propose Retention-Aware Intelligent DRAM Refresh (RAIDR), which reduces refresh overhead by using knowledge of cell retention times.  ... 
doi:10.1109/isorc.2019.00015 dblp:conf/isorc/PanM19 fatcat:rsr56fhzuzcdbpex7pe627rhae

The efficacy of error mitigation techniques for DRAM retention failures

Samira Khan, Donghyuk Lee, Yoongu Kim, Alaa R. Alameldeen, Chris Wilkerson, Onur Mutlu
2014 The 2014 ACM international conference on Measurement and modeling of computer systems - SIGMETRICS '14  
As DRAM cells continue to shrink, they become more susceptible to retention failures.  ...  DRAM cells that permanently exhibit short retention times are fairly easy to identify and repair through the use of memory tests and row and column redundancy.  ...  RAIDR [27] uses higher refresh rates for rows containing weak cells to avoid retention failures. RAPID [50] uses software remapping to disable pages with potential retention failures.  ... 
doi:10.1145/2591971.2592000 dblp:conf/sigmetrics/KhanLKAWM14 fatcat:lwksattf5nblrnhslwb4uymfye

PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM

Samira Khan, Donghyuk Lee, Onur Mutlu
2016 2016 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)  
We introduce a new mechanism that utilizes PARBOR to reduce refresh rate based on the data content of memory locations, thereby improving system performance and efficiency.  ...  DRAM vendors internally scramble/remap the system-level address space.  ...  On average, DC-REF improves system performance by 18.0% for 32Gbit DRAM across all 32 workloads. 6 Compared to RAIDR [46] , a refresh reduction technique that refreshes all rows with weak cells using  ... 
doi:10.1109/dsn.2016.30 dblp:conf/dsn/KhanLM16 fatcat:szqposuj5jcphh47mu5bj5rbri

Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications [article]

Hasan Hassan, Yahya Can Tugrul, Jeremie S. Kim, Victor van der Veen, Kaveh Razavi, Onur Mutlu
2021 arXiv   pre-print
U-TRR is based on the new observation that data retention failures in DRAM enable a side channel that leaks information on how TRR refreshes potential victim rows.  ...  To protect against RowHammer, vendors commit to security-through-obscurity: modern DRAM chips rely on undocumented, proprietary, on-die mitigations, commonly known as Target Row Refresh (TRR).  ...  Mutlu, “RAIDR: Retention-Aware Intelligent com/CMU-SAFARI/rowhammer. DRAM Refresh,” in ISCA, 2012.  ... 
arXiv:2110.10603v1 fatcat:ab7zgdwb3vaqtbszjmyxuvngny

Processing Data Where It Makes Sense: Enabling In-Memory Computation [article]

Onur Mutlu, Saugata Ghose, Juan Gómez-Luna, Rachata Ausavarungnirun
2019 arXiv   pre-print
As a result, memory system architects are open to organizing memory in different ways and making it more intelligent, at the expense of higher cost.  ...  The emergence of 3D-stacked memory plus logic as well as the adoption of error correcting codes inside DRAM chips, and the necessity for designing new solutions to serious reliability and security issues  ...  As shown by a recent body of work whose aim is to design such an intelligent memory controller that can perform inline profiling of DRAM cell retention times and online adjustment of refresh rate on a  ... 
arXiv:1903.03988v1 fatcat:l2sl2wqwmrejvfbi3sxrpwasby
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