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Queue Register File Optimization Algorithm for QueueCore Processor

Arquimedes Canedo, Ben Abderazek, Masahiro Sowa
2007 19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'07)  
In this paper we propose a compiler technique to optimize the queue utilization for the hungry statements that require a large amount of queue.  ...  We show that for SPEC CINT95 benchmarks, our technique optimizes the queue length without decreasing parallelism. However, our optimization has a penalty of a slight increase in code size.  ...  an algorithm to optimize the queue length for the QueueCore processor.  ... 
doi:10.1109/sbac-pad.2007.10 dblp:conf/sbac-pad/SilvaD07 fatcat:d4z2j6xu2jcaze477gpp3r7owm

Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture

Ben Abdallah Abderazek, Masashi Masuda, Arquimedes Canedo, Kenichi Kuroda
2010 Journal of Supercomputing  
Compiling for the QueueCore requires a new approach since the concept of registers disappears. We propose a new efficient code generation algorithm for the QueueCore.  ...  This work presents a static method implemented in a compiler for extracting high instruction level parallelism for the 32-bit QueueCore, a queue computationbased processor.  ...  The queue compiler exposes natural ILP from the input programs to the QueueCore processor.  ... 
doi:10.1007/s11227-010-0409-z fatcat:bkijujepezcfxhek2visg4fpw4

New Code Generation Algorithm for QueueCore An Embedded Processor with High ILP

Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2007 Eighth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2007)  
This paper presents a new code generation scheme for the QueueCore, a 32-bit queue-based architecture capable of executing high amounts of ILP.  ...  Compiling for the QueueCore requires that all instructions have at most one explicit operand represented as an offset calculated at compile-time.  ...  The resulting compiler mapped the operand queue in terms of general purpose registers in the machine description file.  ... 
doi:10.1109/pdcat.2007.12 dblp:conf/pdcat/CanedoAS07 fatcat:edxkom62jveatatyhcme6tvv64

New Code Generation Algorithm for QueueCore An Embedded Processor with High ILP

Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
2007 Eighth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2007)  
This paper presents a new code generation scheme for the QueueCore, a 32-bit queue-based architecture capable of executing high amounts of ILP.  ...  Compiling for the QueueCore requires that all instructions have at most one explicit operand represented as an offset calculated at compile-time.  ...  The resulting compiler mapped the operand queue in terms of general purpose registers in the machine description file.  ... 
doi:10.1109/pdcat.2007.4420170 fatcat:hoyv7exapzcj3avb6yo765sb34

Single Instruction Dual-Execution Model Processor Architecture

Taichi Maekawa, Ben A. Abderazek, Kenichi Kuroda
2008 2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing  
We present in this paper architecture and preliminary evaluation results of a novel dual-mode processor architecture which supports queue and stack computation models in a single core.  ...  It is based on a reduced bit produced order queue computation instruction set architecture and functions into Queue or Stack execution models.  ...  The base Queuec-Core/PQP processor is based on produced order queue computation model and uses a circular queue-register (QREG) for intermediate data.  ... 
doi:10.1109/euc.2008.116 dblp:conf/euc/MaekawaAK08 fatcat:hk6vcgwpznbsbio4y2khi6xtoe

Processor for Mobile Applications [chapter]

Ben Abdallah Abderazek, Arquimedes Canedo, Kenichi Kuroda
Handbook of Research on Mobile Multimedia, Second Edition  
The QueueCore processor is a novel produced order parallel queue processor architecture, which stores intermediate results in a circular queue-registers instead of random access registers.  ...  Thus, the QueueCore processor has a good future in mobile applications world. The QueueCore supports a subset of the produced order queue processor instruction set architecture [4] .  ...  Our future efforts are focused towards the development of algorithms to generate highly optimized code for mobile queue processors [27] .  ... 
doi:10.4018/978-1-60566-046-2.ch035 fatcat:oqr5mg5ahjadplgjnw43co2cqy

Scalable Core-Based Methodology and Synthesizable Core for Systematic Design

B.A. Abderazek, T. Yoshinaga, M. Sowa
2006 International Conference on Parallel Processing Workshops (ICPPW'06)  
., QueueCore (QC-2), GPPs), hardware blocks, memo-  ...  We also developed a high performance 32-bit Synthesizable QueueCore (QC-2) with single precision floating point support.  ...  QC-2 core architecture We proposed in [5, 6] a produced order parallel Queue processor (QueueCore) architecture.  ... 
doi:10.1109/icppw.2006.69 dblp:conf/icppw/AbderazekYS06 fatcat:dzs3zviclna6ndqn54osee7y7y