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Quasi-Pipelined Hash Circuits
17th IEEE Symposium on Computer Arithmetic (ARITH'05)
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Quasi-pipelining could be as well applied to future hashing algorithms, provided they are designed along the same lines as those of the SHA family. ...
We focus particularly on the class of dedicated hash functions, whose general construction is presented; the peculiar arrangement of sequential and combinational units makes the application of pipelining ...
The SHA-1 quasi-pipelined circuit. ...
doi:10.1109/arith.2005.36
dblp:conf/arith/MacchettiD05
fatcat:22pztgfpqjebhldn46wk25vrue
SHA-2 acceleration meeting the needs of emerging applications: A comparative survey
2020
IEEE Access
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INDEX TERMS Accelerators, Hash functions, SHA-2. ...
While SHA-2 is a ubiquitous cryptographic hashing primitive, its role in emerging application domains, e.g. blockchains or trusted IoT components, has made the acceleration of SHA-2 very challenging due ...
FIGURE 6 . 6 Application of Quasi-pipelining in SHA-2: (a) Quasi-pipelined model of SHA-2 with quasi-pipelined sections. (b) Final Quasi-pipelined Sections. ...
doi:10.1109/access.2020.2972265
fatcat:nwbsnwytmjhhnb6by56jhp7ayi
Abnormal Traffic Detection Circuit with Real-time Cardinality Counter
2018
Journal of Information Processing
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By changing the order of the cardinality counting process, the proposed algorithm enables parallel accesses of DRAM circuits, which hides the slow DRAM access time through a pipeline circuit. ...
In addition, we propose a new hashing function that also hides the DRAM access problem. ...
Random access is required for both the quasi-associative memory function and the cache table update because the effective addresses are calculated by hashing. ...
doi:10.2197/ipsjjip.26.590
fatcat:vzf7kbxx3fgztju22enmcvsblu
A Flexible Framework for Exploring, Evaluating, and Comparing SHA-2 Designs
2019
IEEE Access
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In particular, SHA-2 is today a ubiquitous hashing primitive. ...
Its acceleration has driven a wealth of contributions in the technical literature and even a whole industry segment involving dedicated hash processing accelerators. ...
circuit. ...
doi:10.1109/access.2019.2920089
fatcat:ejvkkh5uxjfhdnos3emmyvqfki
A Case for Superconducting Accelerators
[article]
2019
arXiv
pre-print
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Superconducting circuits based on Josephson Junction (JJ) is an emerging technology that can provide devices which can be switched with pico-second latencies and consuming two orders of magnitude lower ...
While JJ-based circuits can provide high operating frequency and energy-efficiency, this technology faces three critical challenges: limited device density and lack of area-efficient technology for memory ...
Whereas, in the quasi-pipelined SHA designs (SHA engine with 4 stage pipeline) each pipeline stage uses a local register [27] . The local register file enables a higher clock rate. ...
arXiv:1902.04641v2
fatcat:eqvbciqawnbi7mcnjghrz5hf5e
A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate Grøstl
2012
2012 15th Euromicro Conference on Digital System Design
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transformation Ω is defined as Comments: 1 four instances of AES in parallel needed (non-feedback modes only), 2 Grøstl's output transformation (finalization) will affect short messages throughput, 3 Grøstl's quasi-pipelined ...
Core Interface accepted by the destination circuit at the next rising edge of the clock. Active HIGH. Ω(x) = trunc n (P (x) ⊕ x). ...
doi:10.1109/dsd.2012.8
dblp:conf/dsd/RogawskiG12
fatcat:mbdvhuzq3vgl7nvc46ufois44a
Implementation of High Throughput Extended Tiny Encryption Algorithm Block Cipher in Field Programmable Gate Array
2016
Indian Journal of Science and Technology
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The throughput is increased by 60% when compared to previous systems that use sub pipelining. ...
In previous, they have used pipelining which increases the overhead that is not desirable. The error detection scheme employed in this paper is RERO (Recomputing with Rotated Operand). ...
As soon as the 2nd quasi of this circuit, that is Л 2 , which executes the 1st input, rotated product of 1st input has been given to the 1st quasi of this circuit that is Л 1 . ...
doi:10.17485/ijst/2016/v9i29/90845
fatcat:6f4wqllq6zfzbhhccsaeqeqdkm
A Novel Permutation-Based Hash Mode of Operation FP and the Hash Function SAMOSA
[chapter]
2012
Lecture Notes in Computer Science
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First, we design a novel permutationbased hash mode of operation FP, and analyze its security. ...
We compare the FP mode with other permutation-based hash modes, and observe that it displays the so far best security/rate trade-off. ...
This design is based on the quasi-pipelined basic iterative architecture denoted as x1 (P/Q). ...
doi:10.1007/978-3-642-34931-7_29
fatcat:vclksy6425g63cn32ujp4joc5y
Hardware Implementation of Hash Functions
[chapter]
2011
Introduction to Hardware Security and Trust
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register. • Skein: Eight Threefish rounds unrolled; generic adders. • JH: 320 S-Boxes (one cycle per R8 round); combinational S-Boxes. • SHA-2: No unrolling or quasi-pipelining; generic adders. ...
The algorithm's symmetry allows the exploitation of SIMD instructions and pipelining in processors, which results in compact code in software, or a compact coprocessor circuit suitable for constrained ...
doi:10.1007/978-1-4419-8080-9_2
fatcat:cgxyrhty2jcrbaaknstb5b4vh4
ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs
2010
2010 International Conference on Field Programmable Logic and Applications
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The capabilities of our environment are demonstrated using three examples: two different hardware architectures of the current cryptographic hash function standard, SHA-256, and one architecture of a candidate ...
In hardware these different ways amount to different architectures (such as basic iterative, unrolled, pipelined, quasi-pipelined, etc.), different optimization tricks (such as precomputation, table look-up ...
This effect is caused mostly by the difficulties associated with routing in congested circuits. ...
doi:10.1109/fpl.2010.86
dblp:conf/fpl/GajKARHB10
fatcat:fpjyi7ryovhpvedmkwzlngjaxy
Exploiting coarse-grain verification parallelism for power-efficient fault tolerance
2005
14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05)
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Due to soft errors, the address used in the quasi-invalidation message may be incorrect. ...
To reduce "false-sharing" of hash entries, we choose a prime number to be the size of the hash table (257 in this paper). ...
doi:10.1109/pact.2005.20
dblp:conf/IEEEpact/RashidTHA05
fatcat:ao6f6potzbfkfhqxsx35kqwqdu
Use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidates
2011
2011 International Conference on Field-Programmable Technology
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Fifteen hash functions, including the current American hash standard SHA-2 and 14 candidates for the new hash standard SHA-3, have been included in our investigation. ...
In this paper, we present results of a comprehensive study devoted to the optimization of FPGA implementations of modern cryptographic hash functions using embedded FPGA resources, such as Digital Signal ...
circuit. ...
doi:10.1109/fpt.2011.6132680
dblp:conf/fpt/ShahidSRG11
fatcat:pqcuwvrnpvamzcfww55hhixq44
DDMPs: self-timed super-pipelined data-driven multimedia processors
1999
Proceedings of the IEEE
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Also outlined here are the numerous advantages, in terms of both function and power consumption, of the self-timed pipeline over its synchronous counterparts. ...
The structure of this paper is as follows: 1) a brief introduction to the data-driven processing principle; 2) a detailed description of elementary modules for the realization of self-timed pipeline microprocessors ...
In the case of a two-operand operation, the matching mechanism can be realized by means of a hash memory in which the hash address is generated by the appropriate manipulation of keys. ...
doi:10.1109/5.740021
fatcat:yxhhlh3fbjavjfelwkrnk6do3e
Variable-Stride Multi-Pattern Matching For Scalable Deep Packet Inspection
2009
IEEE INFOCOM 2009 - The 28th Conference on Computer Communications
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The two traditional methods for increasing system throughput are pipelining and parallelism. ...
The circuit for the winnowing module is very simple and can easily process more than w bytes per clock cycle. ...
doi:10.1109/infcom.2009.5061946
dblp:conf/infocom/HuaSL09
fatcat:pkpdo2j6ubhlnapujdrcizkcea
Massively-Parallel Bit-Serial Neural Networks For Fast Epilepsy Diagnosis: A Feasibility Study
2016
Zenodo
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By using hardware hashing it is possible to minimise the search time. ...
Fig. 7 7 Circuit for the Bit-Adder in this Bit-Serial Processor Fig. 8 Circuit for the Bit-Serial Multiplier in this Processor
Fig. 9 9 Single Waveform of the Multiplication Process of the Nueron Fig ...
doi:10.5281/zenodo.1124672
fatcat:yvvqu3gvgfcofe43cqfvoq7qa4
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