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A Quasi Delay Insensitive Reduced Stack Pre-Charged Half Buffer based High Speed Adder using pipeline templates for Asynchronous Circuits

Jianbo
2012 Journal of Computer Science  
The new templates that provide significant performance improvements in quasi delay insensitivity.  ...  Results: In this study, Quasi Delay Insensitive RSPCHB template has been proposed to enhance the performance is faster with a maximum throughput of 970MHz than the previously designed system.  ...  One important class of asynchronous circuits, which we consider in this study, is Quasi Delay-Insensitive (QDI) circuits.  ... 
doi:10.3844/jcssp.2012.1114.1122 fatcat:6vttjurlwnbsnj2qo42g3s5ldu

Instantly Decodable Network Coding: From Centralized to Device-to-Device Communications

Ahmed Douik, Sameh Sorour, Tareq Y. Al-Naffouri, Mohamed-Slim Alouini
2017 IEEE Communications Surveys and Tutorials  
With the shift toward distributed computing on mobile devices, performance and complexity become both critical factors that affect the efficiency of a coding strategy.  ...  Index Terms-Strict and generalized instantly decodable network coding, completion time, decoding delay, graph theory, maximum weight clique problem, distributed optimization, device-todevice, cooperative  ...  ACKNOWLEDGEMENT The authors wish to thank Professor Parastoo Sadeghi for her helpful comments and suggestions.  ... 
doi:10.1109/comst.2017.2665587 fatcat:mobyvizrd5exhgovnvsbfb667a

Modeling and Optimization of Fringe Capacitance of Nanoscale DGMOS Devices

A. Bansal, B.C. Paul, K. Roy
2005 IEEE Transactions on Electron Devices  
aspects.  ...  Table I shows the delay and energy consumption of the adder implemented with both 50 nm and zerounderlap DGMOS transistors.  ...  scaling issues for bipolar/BiCMOS devices and circuits.  ... 
doi:10.1109/ted.2004.842713 fatcat:ki5vlrqvczegnnbc6kuszrxzky

A unified rlc model for high-speed on-chip interconnects

Sang-Pil Sim, S. Krishnan, D.M. Petranovic, N.D. Arora, Kwyro Lee, C.Y. Yang
2003 IEEE Transactions on Electron Devices  
The model consists of two components, a quasi-three-dimensional (3-D) capacitance model and an effective loop inductance model.  ...  Non-orthogonal wire architecture is also investigated and included in the proposed model.  ...  While there, he had been involved in developing and teaching courses in electrical and computer engineering, as well as in research in the areas of microprocessor system design, digital signal processing  ... 
doi:10.1109/ted.2003.813345 fatcat:ouzu4afdpfe6nazuetrbt6fl3i

Guest editors' introduction: clockless VLSI systems

S. Hassoun, Yong-Bin Kim, F. Lombardi
2003 IEEE Design & Test of Computers  
Design for reuse is a common integration practice for designing SoC implementation at relatively low production costs. Currently,  ...  The most disturbing aspect of this characteristic is that the clock only serves as a timer for computational tasks.  ...  Clockless circuits are at least quasi-delay-insensitive with speed-independent behavior readily applicable to different applications, such as self-timed pipeline designs.  ... 
doi:10.1109/mdt.2003.1246158 fatcat:767q6eliqfchjchnfqchuas4tq

Asynchronous design methodologies: an overview

S. Hauck
1995 Proceedings of the IEEE  
We examine the benefits and problems inherent in asynchronous computations, and in some of the more notable design methodologies.  ...  These include Huffman asynchronous circuits, burst-mode circuits, micropipelines, template-based and trace theory-based delay-insensitive circuits, signal transition graphs, change diagrams, and compilation-based  ...  number of patient readers, including Gaetano Borriello, John Brzozowski, Al Davis, David Dill, Carl Ebeling, Jo Ebergen, Henrik Hulgaard, Carl Seger, Elizabeth Walkup, Steven Nowick, Ivan Sutherland, and  ... 
doi:10.1109/5.362752 fatcat:2wtrcnhd3beeve2vzcuij6vydq

An FPGA for implementing asynchronous circuits

S. Hauck, S. Burns, G. Borriello, C. Ebeling
1994 IEEE Design & Test of Computers  
We describe Montage, the first FPGA to explicitly support asynchronous circuit implementation, and its mapping software.  ...  This is a significant problem because many aspects of glue logic and communication interfaces involve asynchronous elements, or require the interconnection of synchronous components operating under independent  ...  Gaetano Borriello and Carl Ebeling were supported in part by NSF Presidential Young Investigator Awards. Steven Burns was supported in part by an NSF Young Investigator Award.  ... 
doi:10.1109/mdt.1994.303848 fatcat:idjq6igtizhjvdrny2bq777izy

An EDA tool for implementation of low power and secure crypto-chips

Behnam Ghavami, Hossein Pedram, Mehrdad Najibi
2009 Computers & electrical engineering  
In this paper, a fully automated secure design flow and a set of secure library cells resistant to power analysis and fault injection attacks are introduced for quasi delay insensitive asynchronous circuits  ...  To verify the efficiency of our presented design flow, we implemented data encryption standard (DES) and advanced encryption standard (AES) algorithms, and we showed 23% less power consumption compared  ...  Quasi delay insensitive (QDI) circuits are like DI circuits with a weak timing constraint [13] .  ... 
doi:10.1016/j.compeleceng.2008.06.014 fatcat:3bjrexmnbvbilme54efiw64hni

Pressure and stress transients in autoinjector devices

Jean-Christophe Veilleux, Joseph E. Shepherd
2018 Drug Delivery and Translational Research  
The numerical methods described in Appendix A were implemented in Matlab to solve this problem. Figure 2 .8 is a space-time diagram of the computed liquid pressure; this is equivalent to Figure 2.7.  ...  Future Work The work reported in this thesis can be extended in several ways to develop a deeper understanding and study new aspects of the pressure and stress transients in autoinjector devices.  ...  A p p e n d i x B TEST MATRICES The tables in this appendix summarize the successful experiments performed with the in situ methods, the static large-scale autoinjector, and the dynamic large-scale autoinjector  ... 
doi:10.1007/s13346-018-0568-7 pmid:30084014 fatcat:r2kve6jrabfc7g4c3lh4penjam

Computationally Efficient Modelling of Hip Replacement Separation Due to Small Mismatches in Component Centres of Rotation

Lee Etchels, Lin Wang, Mazen Al-Hajjar, Sophie Williams, Jonathan Thompson, Graham Isaac, Ruth Wilcox, Alison Jones
2019 Journal of Biomechanics  
A quick running computational edge loading model (Python Edge Loading (PyEL) - quasi-static, rigid, frictionless), capable of considering realistic bearing geometries, was developed.  ...  The PyEL model agreed well with both the more complex computational modelling and experimental results.  ...  Acknowledgements This study was funded by the UK Engineering and Physical Sciences Research Council (EPSRC -grant EP/N02480X/1); components and CAD files were supplied by DePuy Synthes.  ... 
doi:10.1016/j.jbiomech.2019.07.040 pmid:31431346 fatcat:yitphvaowvfkbpebvw35bgm3ze

IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits

1987 IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.  
devices and circuits, device simulation and optimization and heterostructure field effect transistors.  ...  DISTRIBUTION CODE ABSTRACT (Maximum 200 words) The conference included the following sessions: Plenary" heterojunction bipolar transistors, poster session, resonant tunneling and novel devices, optoelectronic  ...  Acknowledgement The devices, which have been used in this study, have in part been fabricated with the help of the Daimler Benz Research Center Ulm. Many thanks are therefore to C.  ... 
doi:10.1109/cornel.1987.721206 fatcat:kwwfh234a5cx5njrhddhkwhi6e

Theory of latency-insensitive design

L.P. Carloni, K.L. McMillan, A.L. Sangiovanni-Vincentelli
2001 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This allows us to increase the robustness of a design implementation because any delay variations of a channel can be "recovered" by changing the channel latency while the overall system functionality  ...  INTRODUCTION T HE THEORY of latency-insensitive design formally separates communication from computation by defining a system as a collection of computational processes that exchange data by means of communication  ...  Lavagno and A. Saldanha for the discussions that led to the theory of latency-insensitive design. They would also like to thank P. Scaglia for his support and continuous encouragement.  ... 
doi:10.1109/43.945302 fatcat:jdowtgvwpfbldjsrlgulx6s6jy

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

T. Kalavathi Devi, Sakthivel Palaniappan
2015 The Scientific World Journal  
The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB).  ...  This decoder meets the demand of high speed and low power.  ...  Most asynchronous design techniques such as Delay Insensitive (DI), Quasi Delay Insensitive (QDI), speed independent, scalable delay insensitive, bounded delay, and relative timing [3] require some timing  ... 
doi:10.1155/2015/621012 pmid:26558289 pmcid:PMC4617693 fatcat:asyw6jkco5cb3g6oqwbfhaimtm

Robust and Energy-Efficient Hardware: The Case for Asynchronous Design

Ney Laert Vilar Calazans, Taciano Ares Rodolfo, Marcos L. L. Sartori
2021 Journal of Integrated Circuits and Systems  
Asynchronous design and particularly quasi-delay insensitive design promises to deal with the same challenges more gracefully in current advanced nodes, and possibly irrevocably in future technology nodes  ...  producing huge amounts of useful computational work.  ...  ACKNOWLEDGMENTS This research was partially funded by CAPES and CNPq (grant 312917/2018-0), Brazilian funding organizations.  ... 
doi:10.29292/jics.v16i2.518 fatcat:3o2fynlz6rgrlg44dkz5jxp4dq

Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder [article]

P. Balasubramanian, D.L. Maskell, N.E. Mastorakis
2019 arXiv   pre-print
We present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead adder with redundancy carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero  ...  The adders were implemented using a 32/28nm CMOS technology.  ...  Toms, “Synthesis of quasi-delay-insensitive datapath circuits,” Ph.D. thesis, School of Computer Science, The University of Manchester, UK, 2006. 26. P. Balasubramanian and N.E.  ... 
arXiv:1903.09433v1 fatcat:5vswc63rb5hzrmqlea23hxxubu
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