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Optical interconnection networks for high-performance computing systems

Aleksandr Biberman, Keren Bergman
2012 Reports on progress in physics (Print)  
The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems  ...  Enabled by silicon photonic technology, optical interconnection networks have the potential to be a key disruptive technology in computing and communication industries.  ...  in achieving performance gains in computing systems.  ... 
doi:10.1088/0034-4885/75/4/046402 pmid:22790508 fatcat:3nyeayt7l5di3grpw6mgjt4znq

Reports on Progress in Physics

1968 Physics Bulletin  
The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems  ...  Enabled by silicon photonic technology, optical interconnection networks have the potential to be a key disruptive technology in computing and communication industries.  ...  in achieving performance gains in computing systems.  ... 
doi:10.1088/0031-9112/19/10/015 fatcat:zwgqqotpo5bznfnqonk4diu4te

Reports on progress in physics

1964 Nuclear Physics  
The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems  ...  Enabled by silicon photonic technology, optical interconnection networks have the potential to be a key disruptive technology in computing and communication industries.  ...  in achieving performance gains in computing systems.  ... 
doi:10.1016/0029-5582(64)90291-3 fatcat:nukswtihqvemrnmtfvttv2plya

Reports on Progress in Physics

1939 Nature  
The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems  ...  Enabled by silicon photonic technology, optical interconnection networks have the potential to be a key disruptive technology in computing and communication industries.  ...  in achieving performance gains in computing systems.  ... 
doi:10.1038/143833a0 fatcat:xc7y6mpxqrdhllrt35twxj6hye

Reports on progress in physics

L. R.
1962 Nuclear Physics  
The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems  ...  Enabled by silicon photonic technology, optical interconnection networks have the potential to be a key disruptive technology in computing and communication industries.  ...  in achieving performance gains in computing systems.  ... 
doi:10.1016/0029-5582(62)90796-4 fatcat:mggxvkfgcfapvmo4gb6m5z2fcq

Reports on Progress in Physics

1936 Nature  
The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems  ...  Enabled by silicon photonic technology, optical interconnection networks have the potential to be a key disruptive technology in computing and communication industries.  ...  in achieving performance gains in computing systems.  ... 
doi:10.1038/137597a0 fatcat:zelvhihbrbbctbi5dnxhdcdaua

Exploration of photonic networks on chip with the University of Ferrara

Marta Ortín
1970 Jornada de Jóvenes Investigadores del I3A  
Modern chips include several processors that communicate through an interconnection network, which has a direct impact on system performance, power consumption and chip area.  ...  We plan to explore this state-of-the-art field during an internship in the University of Ferrara.  ...  One of the most common and efficient designs are Chip Multiprocessors (CMPs), which include in a single chip several processors that share the memory hierarchy through an interconnection network [1, 2  ... 
doi:10.26754/jji-i3a.201401741 fatcat:js4p3tbpxrhcnevexzzxbull5q

Packetization and routing analysis of on-chip multiprocessor networks

Terry Tao Ye, Luca Benini, Giovanni De Micheli
2004 Journal of systems architecture  
Different packetization schemes affect the performance and power consumption of multiprocessor systems. Our analysis is also quantified by the network/multiprocessor co-simulation benchmark results.  ...  They differ from traditional networks because of larger on-chip wiring resources and flexibility, as well as constraints on area and energy consumption (in addition to performance requirements).  ...  In multiprocessor systems-on-chip, the performance of node processors is closely coupled with the interconnect networks.  ... 
doi:10.1016/j.sysarc.2003.07.005 fatcat:7cojsp4t6refhe35a7xlisxsxq

Design, Synthesis, and Test of Networks on Chips

P.P. Pande, C. Grecu, A. Ivanov, R. Saleh, G. De Micheli
2005 IEEE Design & Test of Computers  
of design requirements that must be fulfilled to achieve a certain performance level.  ...  Researchers have proposed various fault-tolerant multiprocessor architectures and routing algorithms in the parallel processing domain.  ... 
doi:10.1109/mdt.2005.108 fatcat:ftg32fzp2jelppgskbqb34ehiy

A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters

A Rahimi, I Loi, M R Kakoee, L Benini
2011 2011 Design, Automation & Test in Europe  
We designed a parametric, fully combinational Mesh-of-Trees (MoT) interconnection network to support high-performance, single-cycle communication between processors and memories in L1-coupled processor  ...  Our interconnect IP is described in synthesizable RTL and it is coupled with a design automation strategy mixing advanced synthesis and physical optimization to achieve optimal delay, power, area (DPA)  ...  The performance of most digital systems today is indeed interconnect-limited, and the design of a high performance on-chip interconnection network is crucial, as the performance impact due to the latency  ... 
doi:10.1109/date.2011.5763085 dblp:conf/date/RahimiLKB11 fatcat:6khccmo46vhovcemeijsvszu34

Exploiting global knowledge to achieve self-tuned congestion control for k-ary n-cube networks

M. Thottethodi, A.R. Lebeck, S.S. Mukherjee
2004 IEEE Transactions on Parallel and Distributed Systems  
Network performance in tightly-coupled multiprocessors typically degrades rapidly beyond network saturation.  ...  A combination of these two techniques provides high performance under heavy load, does not penalize performance under light load, and gracefully adapts to changes in communication patterns.  ...  BACKGROUND AND RELATED WORK High performance interconnection networks in tightly coupled multiprocessors can be achieved by using wormhole [7] , [6] or cut-through switching [18] , adaptive routing  ... 
doi:10.1109/tpds.2004.1264810 fatcat:75euurmvifhz5gu4xrr3hs4ugu

CDMA as a multiprocessor interconnect strategy

R.H. Bell, Chang Yong Kang, L. John, E.E. Swartzlander
2001 Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256)  
A binary CDMA bus is proposed as a communications interconnect for multiprocessor systems.  ...  The binary CDMA bus is a digital bus which incorporates spreadspectrum technology to encode multiple data streams in parallel onto the same physical interconnect.  ...  In this paper we describe the binary CDMA bus interconnect and quantify the benefits of the technique for a multiprocessor system.  ... 
doi:10.1109/acssc.2001.987690 fatcat:kmrdma63nrbo7nyvkmtzqx5ixu

A case for globally shared-medium on-chip interconnect

Aaron Carpenter, Jianyun Hu, Jie Xu, Michael Huang, Hui Wu
2011 SIGARCH Computer Architecture News  
Packet-switched networks fit the bill for the interconnect needs: existing routers can be directly used in multiple system designs and configurable routing tables allow easy customization for a scalable  ...  For example, the advantage of off-the-shelf interconnect and the in-field scalability of the interconnect are less important in a chip-multiprocessor.  ...  achieves better performance on average than a canonical mesh interconnect (1.17x in an 8-node 16core system).  ... 
doi:10.1145/2024723.2000097 fatcat:d2vuqmnfvbfavpf6mdcdmrvbfi

A case for globally shared-medium on-chip interconnect

Aaron Carpenter, Jianyun Hu, Jie Xu, Michael Huang, Hui Wu
2011 Proceeding of the 38th annual international symposium on Computer architecture - ISCA '11  
Packet-switched networks fit the bill for the interconnect needs: existing routers can be directly used in multiple system designs and configurable routing tables allow easy customization for a scalable  ...  For example, the advantage of off-the-shelf interconnect and the in-field scalability of the interconnect are less important in a chip-multiprocessor.  ...  achieves better performance on average than a canonical mesh interconnect (1.17x in an 8-node 16core system).  ... 
doi:10.1145/2000064.2000097 dblp:conf/isca/CarpenterHXHW11 fatcat:a26wsnidfjbatowabf3alsjgq4

Networks-on-Chip: Emerging Research Topics and Novel Ideas

Davide Bertozzi, Shashi Kumar, Maurizio Palesi
2007 VLSI design (Print)  
In contrast, state-of-the-art interconnect fabrics will soon incur severe scalability limitations.  ...  In the last few years, a number of advances in on-chip interconnect architectures have tried to relieve the limitations of the communication sub-system.  ...  They show how considerable enhancements in fault tolerance can be achieved at the cost of performance and area, and with only a slight increase in power consumption.  ... 
doi:10.1155/2007/26454 fatcat:xqa4mh54fjcjfesipyeqkevrw4
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