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HARDWARE IMPLEMENTATION DESIGN OF A SPIKING NEURON

Alexey Gnilenko
2021 System technologies  
The hardware implementation of an artificial neuron is the key problem of the design of neuromorphic chips which are new promising architectural solutions for massively parallel computing.  ...  The design of the neuron is performed at the transistor level based on Leaky Integrate-and-Fire neuron implementation model. The neuron is simulated using EDA tool to verify the design.  ...  In a pulsed neural network, signals between neurons are transmitted in the form of short pulses -spikes.  ... 
doi:10.34185/1562-9945-1-132-2021-10 fatcat:koktxtt4dbb6tayn5ffogebtou

Silicon modeling of pitch perception

J. Lazzaro, C. Mead
1989 Proceedings of the National Academy of Sciences of the United States of America  
Chip output approximates human performance in response to a variety of classical pitch-perception stimuli.  ...  The chip is a physiological model; subcircuits on the chip correspond to known and proposed structures in the auditory system.  ...  Lyon for valuable contributions throughout the project. We thank R. Lyon  ... 
doi:10.1073/pnas.86.23.9597 pmid:2594787 pmcid:PMC298545 fatcat:pvahkebz2bfn5f6f6unjdvquca

A digital architecture employing stochasticism for the simulation of Hopfield neural nets

D.E. Van Den Bout, T.K. Miller
1989 IEEE Transactions on Circuits and Systems  
Abstruct -A digital architecture which uses stochastic logic for simulating the behavior of Hopfield neural networks is described.  ...  gains with noise from stochastic arithmetic), high execution speecLF ( = N.108 connections per second), expMdability (by cascading of multiple chips to host large networks), and practiculity (by building  ...  U Y = vz The use of random numbers also confers significant advantages. For example, the neural firing comparator pulses only when R, < U and thus has a mean output voltage of ( U ) = l .  ... 
doi:10.1109/31.31321 fatcat:xblswhcdg5gx7ngpbz4ijfrbxq

An auto-scaling wide dynamic range current to frequency converter for real-time monitoring of signals in neuromorphic systems [article]

Ning Qiao, Giacomo Indiveri
2019 arXiv   pre-print
We demonstrate how the circuit is suitable for measuring neural dynamics by showing the converted response properties of the chip silicon neurons and synapses as they are stimulated by input spikes.  ...  Neuromorphic systems typically employ current-mode circuits that model neural dynamics and produce output currents that range from few pico-Amperes to hundreds of micro-Amperes.  ...  Fig. 3 . 3 Die micro-photograph of the test chip with 6 CFC channels (circled in blue) interfaced to different neuromorphic neuron/synapse arrays, for real-time monitoring of neural dynamics.  ... 
arXiv:1908.06545v1 fatcat:rvl45car5baldfn4res53jpqrm

Page 380 of Neural Computation Vol. 4, Issue 3 [page]

1992 Neural Computation  
Pulse-firing neural chips for hundreds of neurons. In Neural Information Processing Systems (NIPS) Conference, pp. 785-792. Morgan Kaufmann, San Mateo, CA. Murray, A.  ...  We are currently testing the scheme’s capabilities more exhaustively, in preparation for full imple- mentation using analog pulse-firing VLSI, in conjunction with dynamic weight and target storage, and  ... 

Single Flux Quantum Based Ultrahigh Speed Spiking Neuromorphic Processor Architecture [article]

Ali Bozbey, Mustafa Altay Karamuftuoglu, Sasan Razmkhah, Murat Ozbayoglu
2020 arXiv   pre-print
We experimentally demonstrate the soma part of the JJ-Neuron for various activation functions together with peripheral SFQ logic gates.  ...  Then, the neural network is trained for the IRIS dataset and we have shown 100 results of the offline training with 1.2x10^10 synaptic operations per second (SOPS) and 8.57x10^11 SOPS/W performance and  ...  Acknowledgements Authors would like to thank Eren Can Aydogan for providing the counter, Yigit Tukel for developing the original PSO algorithm for SFQ circuits used in this study.  ... 
arXiv:1812.10354v3 fatcat:vcivrsruh5edbb55qmds2armmy

Pulse-based signal compression for implanted neural recording systems

John G. Harris, Jose C. Principe, Justin C. Sanchez, Du Chen, Christy She
2008 2008 IEEE International Symposium on Circuits and Systems  
A hardware spiking neuron on each channel is configured either to transmit pulses for full reconstruction on the back-end, or to transmit dramatically fewer pulses but still allow for spike sorting on  ...  Spike sorting is an important step that provides a labeling to multiple neurons on each channel and further improves the accuracy of spike detection.  ...  ACKNOWLEDGMENT The authors gratefully acknowledge funding from NINDS (Grant #NS053561) and NSF (Grant #0541241), and also the work of numerous other students in the lab, in particular J. Xu, M.  ... 
doi:10.1109/iscas.2008.4541425 dblp:conf/iscas/HarrisPSCS08 fatcat:bdeyurkg4zddzh7knxhjx7hzm4

Accelerated Analog Neuromorphic Computing [article]

Johannes Schemmel, Sebastian Billaudelle, Phillip Dauer, Johannes Weis
2020 arXiv   pre-print
Thereby, BSS-2 supports inference of deep convolutional networks as well as local-learning with complex ensembles of spiking neurons within the same substrate.  ...  This allows the integration of a digital plasticity processing unit, a highly-parallel micro processor specially built for the computational needs of learning in an accelerated analog neuromorphic systems  ...  Instead of using the firing history, in HAGEN mode the pulse length is transmitted together with the pre-synaptic spike and converted into variable length pulses by the existing Short Time Plasticity (  ... 
arXiv:2003.11996v1 fatcat:xsljazavgvejhocjjxhv3t7c44

Analog circuits for mixed-signal neuromorphic computing architectures in 28 nm FD-SOI technology [article]

Ning Qiao, Giacomo Indiveri
2019 arXiv   pre-print
with the environment in real-time, and for high-frequency operation for fast data processing in different types of spiking neural network architectures.  ...  We describe the techniques used for maximizing density with mixed-mode analog/digital synaptic weight configurations, and the methods adopted for minimizing the effect of channel leakage current, in order  ...  Fig. 5 shows the combined synapse-neuron transfer function, consisting of the neuron output firing rate as a function of the synapse input firing rate, for three different synaptic efficacy levels (which  ... 
arXiv:1908.07874v1 fatcat:2nnjvyxmlfdsrpua2jpofspn7a

Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain [article]

Chetan Singh Thakur, Jamal Molin, Gert Cauwenberghs, Giacomo Indiveri, Kundan Kumar, Ning Qiao, Johannes Schemmel, Runchun Wang, Elisabetta Chicca, Jennifer Olson Hasler, Jae-sun Seo, Shimeng Yu, Yu Cao, André van Schaik, Ralph Etienne-Cummings
2018 arXiv   pre-print
Building hardware neural emulators can be extremely useful for simulating large-scale neural models to explain how intelligent behavior arises in the brain.  ...  Thus, compared to conventional CPUs, these neuromorphic emulators are beneficial in many engineering applications such as for the porting of deep learning algorithms for various recognitions tasks.  ...  The 2DIFWTA chip: a 2D array of integrate-and-fire neurons for implementing cooperative-competitive networks A competitive network typically consists of a group of interacting neurons, which compete with  ... 
arXiv:1805.08932v1 fatcat:xqtzbpp5ubhfrpfhj6sjffi6ii

A Functional Spiking Neural Network of Ultra Compact Neurons

Pablo Stoliar, Olivier Schneegans, Marcelo J. Rozenberg
2021 Frontiers in Neuroscience  
We demonstrate that recently introduced ultra-compact neurons (UCN) with a minimal number of components can be interconnected to implement a functional spiking neural network.  ...  We then interconnect two of those neurons to an output layer of UCNs, which detect coincidences between spikes propagating down the long-axons.  ...  Yger for valuable discussions. We also thank F. Simon for his help concerning LTspice.  ... 
doi:10.3389/fnins.2021.635098 pmid:33716656 pmcid:PMC7947689 fatcat:24mynsqfqjblrnyzmdkvp3pzle

A Systematic Method for Configuring VLSI Networks of Spiking Neurons

Emre Neftci, Elisabetta Chicca, Giacomo Indiveri, Rodney Douglas
2011 Neural Computation  
An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically  ...  models of neurons and their networks.  ...  Fasnacht for the design of the AER monitor/sequencer board and the reviewers for their useful comments.  ... 
doi:10.1162/neco_a_00182 pmid:21732859 fatcat:pqna5o5okjbqnpo7jzi6tyrduu

Tunable neuromimetic integrated system for emulating cortical neuron models

Filippo Grassia
2011 Frontiers in Neuroscience  
In previous work, we designed several neuromimetic chips, including the Galway chip that we used for this paper.  ...  These silicon neurons are based on the Hodgkin-Huxley formalism and they are optimized for reproducing a large variety of neuron behaviors thanks to tunable parameters.  ...  Philippe Pouliquen for proofreading the material.  ... 
doi:10.3389/fnins.2011.00134 pmid:22163213 pmcid:PMC3233664 fatcat:pfqfbkerovfvlce2dy3p27atea

Synaptic Dynamics in Analog VLSI

Chiara Bartolozzi, Giacomo Indiveri
2007 Neural Computation  
Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatio-temporal spike patterns  ...  Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns  ...  The chip was fabricated via the EUROPRACTICE service. We thank Pratap Kumar for fruitful discussions about biological synapses.  ... 
doi:10.1162/neco.2007.19.10.2581 pmid:17716003 fatcat:64ka3uerlzb4dgic36ygvwlh4e

A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses

Ning Qiao, Hesham Mostafa, Federico Corradi, Marc Osswald, Fabio Stefanini, Dora Sumislawska, Giacomo Indiveri
2015 Frontiers in Neuroscience  
In this paper we present a full-custom mixed-signal VLSI device with neuromorphic learning circuits that emulate the biophysics of real spiking neurons and dynamic synapses for exploring the properties  ...  The proposed architecture allows the on-chip configuration of a wide range of network connectivities, including recurrent and deep networks, with short-term and long-term plasticity.  ...  Sadique Sheik for their helpful comments on the overall chip architecture, Hongzhi You for his work on minimizing mismatch in the silicon neuron circuit, Giovanni Rovere for designing the rail-to-rail  ... 
doi:10.3389/fnins.2015.00141 pmid:25972778 pmcid:PMC4413675 fatcat:oxoslvrbyneiraxcqcod5jphm4
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