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ReStore: Symptom-Based Soft Error Detection in Microprocessors

N.J. Wang, S.J. Patel
2006 IEEE Transactions on Dependable and Secure Computing  
This will not be the case for long, and questions remain as to the best way to detect and recover from soft errors in the remainder of the processor -in particular, the less structured execution core.  ...  Error detection in the ReStore architecture is novel: symptoms that hint at the presence of soft errors trigger restoration of a previous checkpoint.  ...  Being able to detect the presence of soft errors enables dynamic fine tuning of the symptom based mechanism.  ... 
doi:10.1109/tdsc.2006.40 fatcat:lsq55w3zl5guxohv4mvlvwb5pi

Mocklinter: Linting Mutual Exclusive Deadlocks with Lock Allocation Graphs

Zhen Yu, Xiaohong Su, Tiantian Wang, Peijun Ma
2016 International Journal of Hybrid Information Technology  
Mocklinter uses this graph to decide whether a deadlock is confronted or not. Mocklinter handles all types of pthread mutexes and can detect any number of deadlocks at a time.  ...  We present Mocklinter, a dynamic deadlock detection tool to capture a deadlock as soon as it happens and spit out enough information to support source-level debugging.  ...  We thank the anonymous reviewers for useful feedback, Yan Cai in City University of HongKong for discussing how to reproduce the bug#37080 in MySQL, Aaron Richton in Rutgers, The State University of New  ... 
doi:10.14257/ijhit.2016.9.3.34 fatcat:yz4kgyeetjcwjpzseyk3v64fne

Characterizing the effects of transient faults on a high-performance processor pipeline

N.J. Wang, J. Quek, T.M. Rafacz, S.J. Patel
2004 International Conference on Dependable Systems and Networks, 2004  
These failures were analyzed to identify the most vulnerable portions of the processor, which were then protected using simple low-overhead techniques. This resulted in a 75% reduction in failures.  ...  To perform a thorough exploration, a highly detailed register transfer level model of a deeply pipelined, out-of-order microprocessor was created.  ...  This study is conducted on a latch-accurate Verilog model of a modern wide-issue Alpha processor that uses speculative execution.  ... 
doi:10.1109/dsn.2004.1311877 dblp:conf/dsn/WangQRP04 fatcat:szmof2m3bzaj5bxwyoupiembki

RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance

Shidhartha Das, Carlos Tokunaga, Sanjay Pant, Wei-Hsiang Ma, Sudherssen Kalaiselvan, Kevin Lai, David M. Bull, David T. Blaauw
2009 IEEE Journal of Solid-State Circuits  
We implement a 64-bit processor in 0.13 m technology which uses RazorII for SER tolerance and dynamic supply adaptation.  ...  In this paper, we present a design (RazorII) which implements a flip-flop with in situ detection and architectural correction of variation-induced delay errors.  ...  Hence, it is required to monitor the instruction being replayed to detect a deadlock situation.  ... 
doi:10.1109/jssc.2008.2007145 fatcat:3l5rk6w375abldfl3mmezk5jua

Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance

David Blaauw, Sudherssen Kalaiselvan, Kevin Lai, Wei-Hsiang Ma, Sanjay Pant, Carlos Tokunaga, Shidhartha Das, David Bull
2008 Digest of technical papers / IEEE International Solid-State Circuits Conference  
We implement a 64-bit processor in 0.13 m technology which uses RazorII for SER tolerance and dynamic supply adaptation.  ...  In this paper, we present a design (RazorII) which implements a flip-flop with in situ detection and architectural correction of variation-induced delay errors.  ...  Hence, it is required to monitor the instruction being replayed to detect a deadlock situation.  ... 
doi:10.1109/isscc.2008.4523226 dblp:conf/isscc/BlaauwKLMPTDB08 fatcat:g7wmfbxidrgvnfafwgdmx7gyhu

Static Deadlock Detection for Java Libraries [chapter]

Amy Williams, William Thies, Michael D. Ernst
2005 Lecture Notes in Computer Science  
To this end, we propose a method for static detection of deadlock in Java libraries.  ...  Our flow-sensitive, context-sensitive analysis determines possible deadlock configurations using a lock-order graph. This graph represents the order in which locks are acquired by the library.  ...  This work is supported in part by NSF grant CCR-0133580, the MIT-Oxygen Project, and an NSF Graduate Research Fellowship. telligently respond to deadlock in a library component.  ... 
doi:10.1007/11531142_26 fatcat:6j3y6vuqzvc25gkjnialvk3lbu

A Survey on Hardware and Software Support for Thread Level Parallelism [article]

Somnath Mazumdar, Roberto Giorgi
2016 arXiv   pre-print
In this paper, first, we have given an overview of threads, threading mechanisms and its management issues during execution.  ...  Hardware support at execution time is very crucial to the performance of the system, thus different types of hardware support for threads also exist or have been proposed, primarily based on widely used  ...  -Tools for detecting deadlocks: MagicFuzzer [CC12], [NPSG09; JPSN09] only for Java, Dreadlocks [KH08], Pulse [LELS05]. ACM Computing Surveys, Vol. X, No.  ... 
arXiv:1603.09274v3 fatcat:75isdvgp5zbhplocook6273sq4

Déjà fu: a concurrency testing library for haskell

Michael Walker, Colin Runciman
2015 Proceedings of the 8th ACM SIGPLAN Symposium on Haskell - Haskell 2015  
This paper introduces a generalisation of Haskell's concurrency abstraction in the form of typeclasses, and a library for testing concurrent programs.  ...  A number of examples are provided, some of which come from pre-existing packages.  ...  Detecting Deadlock Deadlock detection is implemented in GHC as part of garbage collection: if a thread is blocked on a variable to which no running thread has a reference, that thread is deadlocked.  ... 
doi:10.1145/2804302.2804306 dblp:conf/haskell/WalkerR15 fatcat:iuyacokc4bhyrjwtwps7cloxmu

Déjà Fu: a concurrency testing library for Haskell

Michael Walker, Colin Runciman
2015 SIGPLAN notices  
This paper introduces a generalisation of Haskell's concurrency abstraction in the form of typeclasses, and a library for testing concurrent programs.  ...  A number of examples are provided, some of which come from pre-existing packages.  ...  Detecting Deadlock Deadlock detection is implemented in GHC as part of garbage collection: if a thread is blocked on a variable to which no running thread has a reference, that thread is deadlocked.  ... 
doi:10.1145/2887747.2804306 fatcat:rztituni65gpliponpdqqmmpqi

Coverage of a microarchitecture-level fault check regimen in a superscalar processor

Vimal Reddy, Eric Rotenberg
2008 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN)  
A few simple microarchitecture-level fault checks can detect many arbitrary faults in large units, by observing microarchitecture-level behavior and anomalies in this behavior.  ...  This paper provides the culmination by building a full regimen into a superscalar processor.  ...  The issue stage (IS) dynamically schedules instructions for execution based on data availability and issue bandwidth.  ... 
doi:10.1109/dsn.2008.4630065 dblp:conf/dsn/ReddyR08 fatcat:unq3sfknhjbgrnmpcbkjeqjh3y

Operating system support for application-specific speculation

Benjamin Wester, Peter M. Chen, Jason Flinn
2011 Proceedings of the sixth conference on Computer systems - EuroSys '11  
Speculative execution is a technique that allows serial tasks to execute in parallel.  ...  We implement a speculation mechanism in the operating system, where it can coordinate speculations across all applications and kernel state.  ...  Pulse speculatively resumes threads that are waiting for a resource to see if they will deadlock [Li 2005 ].  ... 
doi:10.1145/1966445.1966467 dblp:conf/eurosys/WesterCF11 fatcat:ewxffdfiufg3hnteo4hgj4jrka

Patching Processor Design Errors with Programmable Hardware

Smruti Sarangi, Satish Narayanasamy, Bruce Carneal, Abhishek Tiwari, Brad Calder, Josep Torrellas
2007 IEEE Micro  
Error fingerprint An error fingerprint is used to program the proposed hardware patching mechanism to dynamically detect and recover from a design error.  ...  However, if a processor uses a watchdog timer along with our proposed architecture, our hardware could potentially report the cause for a deadlock when the watchdog timer detects it.  ... 
doi:10.1109/mm.2007.19 fatcat:rwlrv3kykbei3n67badflnzqn4

A survey of checker architectures

Rajshekar Kalayappan, Smruti R. Sarangi
2013 ACM Computing Surveys  
We present a survey of different kinds of fault detection mechanisms for processors at the circuit, architecture, and software level.  ...  To achieve a high degree of fault tolerance, we need to detect faults quickly, and try to rectify them. In this paper, we focus on the former aspect.  ...  When a fault is detected (logical or deadlock), the checker flushes the pipeline of the master.  ... 
doi:10.1145/2501654.2501662 fatcat:rmmc2ntqofgkvnbjhwpmekol4i

Examining ACE analysis reliability estimates using fault-injection

Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel
2007 Proceedings of the 34th annual international symposium on Computer architecture - ISCA '07  
Bounding the reliability of a design is useful since it can guarantee that the given design will meet reliability goals.  ...  ACE analysis couples data from abstract performance models with low level design details to identify and rule out transient faults that will not cause incorrect execution.  ...  The ReStore architecture is low cost because it re-uses existing mechanisms to perform checkpointing and symptom detection.  ... 
doi:10.1145/1250662.1250719 dblp:conf/isca/WangMP07 fatcat:5adwbd5jebd5lk2h5rhpoyakgy

Architectural Techniques for Adaptive Computing [chapter]

Shidhartha Das, David Roberts, David Blaauw, David Bull, Trevor Mudge
2008 Adaptive Techniques for Dynamic Processor Optimization  
Introduction to Razor Razor [28] is a circuit-level timing speculation technique based on dynamic detection and correction of speed path failures in digital designs.  ...  The key idea in Razor II is to use the Razor flip-flop only for error detection. State recovery after a timing error occurs by a conventional replay mechanism from a check-pointed state.  ... 
doi:10.1007/978-0-387-76472-6_8 fatcat:vew4lkjofre6rfsorgavdbz574
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