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Design validation of multithreaded architectures using concurrent threads evolution

D. Ravotto, E. Sanchez, M. Sonza Reorda, G. Squillero
2009 Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design Chip on the Dunes - SBCCI '09  
Basics on OpenSPARC TM processor cores The OpenSPARC TM processor core family is designed exploiting the chip multi-threaded (CMT) processor architecture paradigm.  ...  In this work we propose a simulation-based method able to efficiently exploit high-level descriptions of multithreaded microprocessor cores for generating effective test programs of critical modules.  ... 
doi:10.1145/1601896.1601964 dblp:conf/sbcci/RavottoSRS09 fatcat:fgtiss2sabhobcos22rcj3qx6m

Acceleration of Genetic Algorithms for Sudoku Solution on Many-Core Processors [chapter]

Yuji Sato, Naohiro Hasegawa, Mikiko Sato
2013 Natural Computing Series  
application of evolutionary computation.  ...  In this chapter, we use the problem of solving Sudoku puzzles to demonstrate the possibility of achieving practical processing time through the use of manycore processors for parallel processing in the  ...  Thread Dispatch Fig. 8 The system architecture for multi-core processors.  ... 
doi:10.1007/978-3-642-37959-8_19 fatcat:czz75owyq5bpzbrnefgteg36fm

GPGPU for Difficult Black-box Problems

Marcin Pietroń, Aleksander Byrski, Marek Kisiel-Dorohinicki
2015 Procedia Computer Science  
The presented research is a part of building heterogenous parallel algorithm for difficult black-box Golomb Ruler problem.  ...  In this paper, efficient use of a hardware accelerator to implement dedicated solvers for such problems is discussed and studied based on an example of Golomb Ruler problem.  ...  Acknowledgments The research presented in the paper received partial support from AGH University of Science and Technology statutory project (no. 11.11.230.124).  ... 
doi:10.1016/j.procs.2015.05.249 fatcat:rd6xn7xpinbcxpj75usayumm3i

LINPACK: Power- Performance Analysis of Multi-Core Processors using OpenMP

Vijayalakshmi Saravanan, Mohan Radhakrishnan, Mukund Sankaran, D. P. Kothari
2012 International Journal of Computer Applications  
A major emphasis is given here to find an efficient parallel programming method on multi-core processors for performance and power gains based on the obtained execution time.  ...  The results of multi-core performance are found to be encouraging. General Terms Multi-core Architecture, LINPACK and Parallelization.  ...  Her research interests include Multi-core Low Power Design Exploration, Power-Aware Processor Design, and Computer Architecture.  ... 
doi:10.5120/6068-8224 fatcat:iyh2253uavcmllhfogtirpl3yu

Fast and scalable temperature-driven floorplan design in 3D MPSoCs

Ignacio Arnaldo, Alessandro Vicenzi, Jose L. Ayala, Jose L. Risco, J. Ignacio Hidalgo, Martino Ruggiero, David Atienza
2012 2012 13th Latin American Test Workshop (LATW)  
A comparative study shows that this work outperforms other proposals and reduces the computational time of the thermal optimization of complex architectures.  ...  This paper proposes a fast and scalable CPU-GPU implementation of a multi-objective evolutionary algorithm that performs a thermal optimization of complex 3D MPSoCs, capable of obtaining optimal solutions  ...  CONCLUSION This work has proposed an efficient thermal-aware 3D floorplanner for heterogeneous multi-processor architectures.  ... 
doi:10.1109/latw.2012.6261245 dblp:conf/latw/ArnaldoVARHRA12 fatcat:hhheq6gu25czng7wvchzbh47xe

Improved Multi-Core Real-time Task Scheduling of Reconfigurable Systems with Energy Constraints

Hamza Chniter, Olfa Mosbahi, Mohamed Khalgui, Mengchu Zhou, Zhiwu Li
2020 IEEE Access  
This paper deals with the scheduling of real-time periodic tasks executed on heterogeneous multicore platforms. Each processor is composed of a set of multi-speed cores with limited energy resources.  ...  The potency and effectiveness of the proposed approach are rated through simulation studies.  ...  A power-aware scheduling solution based on a multi-objective evolutionary algorithm is proposed in [6] to optimize a set of criteria such as temperature, energy cost and effectiveness.  ... 
doi:10.1109/access.2020.2990973 fatcat:rd4yxrxgbffpjc5tlo22yooi3i

GPU Parallel Computation in Bioinspired Algorithms: A Review [chapter]

M. G. Arenas, G. Romero, A. M. Mora, P. A. Castillo, J. J. Merelo
2012 Studies in Computational Intelligence  
As bioinspired methods usually need a high amount of computational resources, parallelization is an interesting alternative in order to decrease the execution time and to provide accurate results.  ...  , particularly in the fields of computational biology and bioinformatics.  ...  Now, to manage CPU power dissipation, processor makers favor multi-core chip designs, and software has to be written in a multi-threaded or multi-process manner to take full advantage of the hardware.  ... 
doi:10.1007/978-3-642-30154-4_6 fatcat:hs6jd4uvavcfxl7e374fjcufg4

Solution of Linear and Non-Linear Boundary Value Problems Using Population-Distributed Parallel Differential Evolution

Amnah Nasim, Laura Burattini, Muhammad Faisal Fateh, Aneela Zameer
2019 Journal of Artificial Intelligence and Soft Computing Research  
Hence the need for evolutionary algorithms becomes evident. However, evolutionary algorithms are compute-intensive since they scan the entire solution space for an optimal solution.  ...  In this research a population-distributed implementation for differential evolution algorithm is presented for solving systems of 2nd-order, 2-point boundary value problems (BVPs).  ...  [6] proposed a coarse-grained parallel architecture for an adaptive differential evolution algorithm based on the multi-population random connection topology.  ... 
doi:10.2478/jaiscr-2019-0004 fatcat:qyvv73csizfn7k6bfi5buf7ibm

Using game theory for scheduling tasks on multi-core processors for simultaneous optimization of performance and energy

Ishfaq Ahmad, Sanjay Ranka, Samee Ullah Khan
2008 Proceedings, International Parallel and Distributed Processing Symposium (IPDPS)  
Multi-core processors are beginning to revolutionize the landscape of high-performance computing.  ...  In this paper, we address the problem of power-aware scheduling/mapping of tasks onto heterogeneous and homogeneous multi-core processor architectures.  ...  Examples of such architectures include the IBM Cell Processor, AMD and Intel Multi-core processors [13] . The cores in general will be heterogeneous in time and energy requirements.  ... 
doi:10.1109/ipdps.2008.4536420 dblp:conf/ipps/AhmadRK08 fatcat:4krzdxkrsvhnfj6symdpjiyofi

Parallel and Distributed Optimization of Dynamic Data Structures for Multimedia Embedded Systems [chapter]

José L. Risco-Martín, David Atienza, J. Ignacio Hidalgo, Juan Lanchares
2010 Studies in Computational Intelligence  
We propose a parallel Multi-Objective Evolutionary Algorithm (MOEA) which combines NSGA-II and SPEA2.  ...  In this work, we propose a method that uses parallel processing and evolutionary computation to explore DDTs in the design of embedded applications.  ...  6 A graphic representation of the DEVS model (multi-core architecture) and its evolution over time Fig. 7 . 7 A graphic representation of the DEVS model (multi-core/distributed architecture) Fig. 8  ... 
doi:10.1007/978-3-642-10675-0_12 fatcat:drjtcctg3jc3rnftrpgujw4fjq

ESPACENET: A Framework of Evolvable and Reconfigurable Sensor Networks for Aerospace–Based Monitoring and Diagnostics

T. Arslan, N. Haridas, E. Yang, A.T. Erdogan, N. Barton, A.J. Walton, J.S. Thompson, A. Stoica, T. Vladimirova, K.D. McDonald-Maier, W.G.J. Howells
2006 First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)  
This paper proposes the framework for an Evolvable Sensor Network Architecture, investigated as part of the ESPACENET project, collocated at the University of Edinburgh, Essex, Kent and Surrey.  ...  The aim is to design a flexible and intelligent embedded network of reconfigurable piconodes optimised by a hierarchical multi-objective algorithm.  ...  computations, and true multi-objective algorithms.  ... 
doi:10.1109/ahs.2006.34 dblp:conf/ahs/ArslanHYEBWTSVMH06 fatcat:7wywken2gjb5rn5gr33pygou4i

Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques

Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria
2009 2009 International Symposium on Systems, Architectures, Modeling, and Simulation  
The design space of a Multi-processor architecture is too large to be evaluated comprehensively.  ...  In this paper we propose a methodology for heuristic platform based design based on evolutionary algorithms and multi-level simulation techniques.  ...  We finally present a set of experimental results obtained by applying the proposed platform-based design heuristic to the exploration of a Chip Multi-Processor architecture [5] (with a number of cores  ... 
doi:10.1109/icsamos.2009.5289222 dblp:conf/samos/MarianiPSZ09 fatcat:e47hrs2ozngaze3ufzgpnycbri

Hardware accelerators for biocomputing: A survey

Souradip Sarkar, Turbo Majumder, Ananth Kalyanaraman, Partha Pratim Pande
2010 Proceedings of 2010 IEEE International Symposium on Circuits and Systems  
Various hardware platforms, such as FPGA, Graphics Processing Unit (GPU), the Cell Broadband Engine (CBE) and multi-core processors are being explored.  ...  In this paper, we present a survey of hardware accelerators for biocomputing by choosing a representative set of each. I.  ...  Bakos and Elenis [13] proposed a co-processor design for whole-genome phylogenetic reconstruction using a parallelized version of breakpoint median computation, which is an expensive component of the  ... 
doi:10.1109/iscas.2010.5537736 dblp:conf/iscas/SarkarMKP10 fatcat:abxldburrvcgxe2rs4uhgqr2ka

A Survey of CPU-GPU Heterogeneous Computing Techniques

Sparsh Mittal, Jeffrey S. Vetter
2015 ACM Computing Surveys  
The current availability of heterogeneous architectures including GPU and CPU cores with different power-performance characteristics and mechanisms for dynamic voltage and frequency scaling does, in fact  ...  This paper analyses the energy consumption and runtime behavior of a parallel master-worker evolutionary algorithm according to the workload distribution between GPU and CPU cores and their operation frequencies  ...  Since a scheduling algorithm built on a Pareto-based multi-objective evolutionary algorithm would require a long computing time together with a strategy to select from the different alternatives in the  ... 
doi:10.1145/2788396 fatcat:syf63kygozdvxaafisz6s6l34a

Evolutionary optimization of neural networks with heterogeneous computation: study and implementation

Jorge D. Fe, Ramón J. Aliaga, Rafael Gadea-Gironés
2015 Journal of Supercomputing  
In the optimization of Artificial Neural Networks (ANNs) via Evolutionary Algorithms (EAs) and the implementation of the necessary training for the objective function, there is often a trade-off between  ...  The implementation of the individuals on a remote low-cost Altera FPGA allowed us to obtain a 3x-4x acceleration compared with a 2.83 GHz Intel Xeon Quad-Core and 6x-7x compared with a 2.2GHz AMD Opteron  ...  Acknowledgments The translation of this paper was funded by the Universitat Politècnica de València, Spain  ... 
doi:10.1007/s11227-015-1419-7 fatcat:y2opovhe5neobhnjdfmerz7yza
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