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Field-programmable gate array implementation of low-density parity-check codes decoder and hardware testbed
2013
IEEE 2013 Tencon - Spring
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This paper presents the design, implementation, experimental verification, and validation of the proposed LDPC decoder using a real-time FPGA based baseband test. ...
Understanding its performance in the design and implementation of forward error correction codes in a realtime manner is necessary for rapid prototyping in research areas that are primarily based on emulation ...
ACKNOWLEDGMENT The authors would like to express gratitude towards the Sirindhorn International Thai-German Graduate School of Engineering (TGGS), Bangkok, Thailand for their equipment supports. ...
doi:10.1109/tenconspring.2013.6584426
fatcat:imicyevk2nfyfjtsi53fy2qpdu
Evaluation of H.264/AVC over IEEE 802.11p vehicular networks
2013
EURASIP Journal on Advances in Signal Processing
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In order to improve performance, we propose to substitute the convolutional channel encoder used in IEEE 802.11p for a low-density parity-check code encoder. ...
We present an FPGA-based testbed developed to evaluate H.264/AVC (Advanced Video Coding) video transmission over vehicular networks. ...
-01, and CSD2008-00010. ...
doi:10.1186/1687-6180-2013-77
fatcat:5asbiven2zgy3d4dkbcdbrytzu
Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case
2012
2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines
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OpenCL-based parallel kernels are used without modifications or code tuning on multicore CPUs, GPUs and FPGAs. ...
Hardware designers and engineers typically need to explore a multi-parametric design space in order to find the best configuration for their designs using simulations that can take weeks to months to complete ...
used (the work herein proposed only analyzes the LDPC decoder). ...
doi:10.1109/fccm.2012.46
dblp:conf/fccm/FalcaoONPBAKBI12
fatcat:bh5ywb3csvdafai7sorxzkqq5a
FPGA Implementation of Reduced Complexity LDPC Codes
2018
DJ Journal of Advances in Electronics and Communication Engineering
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These product code scheme uses LDPC code for performing encoding operation and thus the designed fault tolerant system for flash memories is implemented using the programming language Verilog HDL, and ...
This paper proposes an Error Control Coding (ECC) technique in flash memories using FPGA implementation. ...
This paper proposes the design of product based code scheme for NAND based memory by using LDPC codes. ...
doi:10.18831/djece.org/2019011001
fatcat:4t4rihiahnbubj25dqboz35kw4
Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder
2006
IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications
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Furthermore, to suppress the error floor level, a characterization on the conditions for short cycles in a LDPC code matrix expanded from a small base matrix is presented, and a cycle elimination algorithm ...
Index Terms-Block-error rate, channel encoding, cycle elimination, forward error correction (FEC), field-programmable gate array (FPGA), low-density parity-check (LDPC) codes, multi-rate, orthogonal frequency ...
Wang, Oregon State University, Corvallis, for several helpful discussions, and the anonymous reviewers for their constructive comments. ...
doi:10.1109/tcsi.2005.862074
fatcat:2o6d3mhl3zaffovus3rsltkfm4
A Rapid Prototyping Environment for Wireless Communication Embedded Systems
2003
EURASIP Journal on Advances in Signal Processing
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, and computer aided design techniques for simulation, synthesis, verification, and integration of complex systems. ...
., develops an approach for dynamic reconfiguration of FPGA implementations. ...
In addition, we would like to thank Xilinx for donating the FPGA chips and the software tools. ...
doi:10.1155/s111086570330304x
fatcat:3ird7hyyzjeb5bmrqa6ztx7574
Design of a GF(64)-LDPC Decoder Based on the EMS Algorithm
2013
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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The implemented decoder presents performance at less than 0.7 dB from the Belief Propagation algorithm for different code lengths and rates. ...
This paper presents the architecture, performance and implementation results of a serial GF(64)-LDPC decoder based on a reduced-complexity version of the Extended Min-Sum algorithm. ...
To obtain both good error correcting performance and hardware friendly LDPC decoder, we consider the optimized non-binary protograph-based codes [35] [36] with d v = 2 proposed by D. ...
doi:10.1109/tcsi.2013.2279186
fatcat:tjdhkbbewngj3gjhe55a7utdca
The M2DC Project: Modular Microserver DataCentre
2016
2016 Euromicro Conference on Digital System Design (DSD)
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This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs. ...
Since their introduction, FPGAs can be seen in more and more different fields of applications. ...
LDPC code partly parallel decoder
2002
[142]
Communication
Beamforming
2002
[143]
Mathematics
Population based ant colony optimization
2002
[144]
Neuro-computing
Bidirectional associative ...
doi:10.1109/dsd.2016.76
dblp:conf/dsd/CecowskiAOKBCKP16
fatcat:bu4nbkqaejebjafrotibui6mkq
A Survey of FPGA-Based LDPC Decoders
2016
IEEE Communications Surveys and Tutorials
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We offer recommendations that will facilitate fairer comparisons of future designs, as well as opportunities for improving the design of FPGA-based LDPC decoders. ...
This paper explores the key factors involved in FPGA-based LDPC decoder design and presents an extensive review of the current literature. ...
Open-source code can be readily found for many of the signal processing blocks used in communications systems, but unfortunately there are very few freely-available FPGA-based LDPC decoder designs. ...
doi:10.1109/comst.2015.2510381
fatcat:k5a5qdfdprg33cyzlirizvwn7y
Exploring manycore architectures for next-generation HPC systems through the MANGO approach
2018
Microprocessors and microsystems
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Acknowledgements This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 671668. ...
For mapping Example of tile topology on multi-FPGA system of logical and virtual memory addresses, TLB module is used. ...
BRAMs are rarely used in the design (they are in facto not optimized for mapping FPGA resources). ...
doi:10.1016/j.micpro.2018.05.011
fatcat:gf4jczkxgzcpfdbgqygmwbkwfq
A 5-Gbps FPGA prototype of a (31,29)2 Reed-Solomon turbo decoder
2008
2008 5th International Symposium on Turbo Codes and Related Topics
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Thus, a full-parallel turbo decoding architecture dedicated to the (31, 29) 2 RS product code has been designed and then implemented into a 5Gbps experimental setup. ...
In this paper, the use of single-error-correcting Reed-Solomon (RS) product codes are investigated in an ultra highspeed context. ...
Boutillon for providing the WGN IP. They are grateful to R. Le Bidan for providing the optimal bit error performance of iterative decoding of a (31, 29) 2 RS product code. ...
doi:10.1109/turbocoding.2008.4658674
fatcat:nxvo7mo2qraknkxmbocurr2w2i
An SDR-based Satellite Gateway for Internet of Remote Things (IoRT) Applications
2020
IEEE Access
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The proposed architecture leaves space for both the satellite and the terrestrial interfaces to be implemented as FPGA code or by using external COTS modules connected through the interfacing capabilities ...
Following the analysis, MODCOD as the optimal variant for our system. ...
doi:10.1109/access.2020.3004480
fatcat:udef6afoorhlhp76a3oolmnlku
Field Programmable Gate Array Applications—A Scientometric Review
2019
Computation
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These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers' navigation systems ...
Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). ...
The embedded wavelet coding algorithm know as EBCOT (Embedded Block Coding with Optimized Truncation of bit-stream), used for JPEG2000 standard, has been widely implemented in FPGAs for parallel optimization ...
doi:10.3390/computation7040063
fatcat:wxtatzsvvnfopghdfl25hcfc2a
Lowdensity Parity-Check Codes
[chapter]
2015
Fundamentals of Convolutional Coding
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It is shown that probabilistic input to LDPC decoders can be generated based on the derived model and it is also shown that binary and nonbinary LDPC codes can outperform conventional RS or BCH codes using ...
Binary and nonbinary LDPC codes are discussed for both magnetic recording channels and memory systems. ...
It will be shown that binary LDPC codes can outperform BCH and RS codes in single-bit-per-cell memory systems and that nonbinary LDPC codes can outperform BCH and RS codes in multi-bit-per-cell memory ...
doi:10.1002/9781119098799.ch8
fatcat:3eku7giigvc6xiz67ywtpxhhcq
Low-Density Parity-Check Codes
[chapter]
2005
Error Correction Coding
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It is shown that probabilistic input to LDPC decoders can be generated based on the derived model and it is also shown that binary and nonbinary LDPC codes can outperform conventional RS or BCH codes using ...
Binary and nonbinary LDPC codes are discussed for both magnetic recording channels and memory systems. ...
It will be shown that binary LDPC codes can outperform BCH and RS codes in single-bit-per-cell memory systems and that nonbinary LDPC codes can outperform BCH and RS codes in multi-bit-per-cell memory ...
doi:10.1002/0471739219.ch15
fatcat:fpabmcl65nbtfi7pkvgzspnr54
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