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Program counter-based prediction techniques for dynamic power management

C. Gniady, A.R. Butt, Y.C. Hu, Yung-Hsiang Lu
2006 IEEE transactions on computers  
PCAP uses path-based correlation to observe a particular sequence of program counters leading to each idle period and predicts future occurrences of that idle period.  ...  It presents a complete design of Program-Counter Access Predictor (PCAP) that dynamically learns the access patterns of applications and predicts when an I/O device can be shut down to save energy.  ...  ACKNOWLEDGMENTS The authors thank Le Cai for helping them set up the data acquisition card for energy measurement and the anonymous reviewers for their helpful comments.  ... 
doi:10.1109/tc.2006.87 fatcat:kz4yv2lxebd45ny5w5dz66n4gm

Program Counter Based Techniques for Dynamic Power Management

C. Gniady, Y.C. Hu, Yung-Hsiang Lu
10th International Symposium on High Performance Computer Architecture (HPCA'04)  
PCAP uses path-based correlation to observe a particular sequence of program counters leading to each idle period, and predicts future occurrences of that idle period.  ...  The paper presents a complete design of Program-Counter Access Predictor (PCAP) that dynamically learns the access patterns of applications and predicts when an I/O device can be shut down to save energy  ...  PCAP We propose Program Counter based Access Predictor (PCAP), a new dynamic prediction method that can accurately predict idle periods.  ... 
doi:10.1109/hpca.2004.10021 dblp:conf/hpca/GniadyHL04 fatcat:kej7jmishzhexcoaa74wgolbja

Workload characterization and prediction: A pathway to reliable multi-core systems

Monir Zaman, Ali Ahmadi, Yiorgos Makris
2015 2015 IEEE 21st International On-Line Testing Symposium (IOLTS)  
Traditionally, reactive thermal/power management techniques have been used to take appropriate action when the temperature reaches a threshold.  ...  Our results show that the proposed method forecasts workload dynamics and power very accurately and outperforms previous prediction techniques.  ...  Dynamic power and thermal management have been introduced to address this issue.  ... 
doi:10.1109/iolts.2015.7229843 dblp:conf/iolts/ZamanAM15 fatcat:knqswqgmvrgplalqnr7gkw7veu

ESKIMO

Ciji Isen, Lizy John
2009 Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture - Micro-42  
Dynamic Random Access Memory (DRAM) is used as the bulk of the main memory in most computing systems and its energy and power consumption has become a first-class design consideration for modern systems  ...  We evaluate the energy and power benefits of our technique using a publicly available, hardware-validated, DRAM simulator, DRAMsim [1].  ...  We make use of the program semantic observations resulting from memory management. Most program languages provide means for dynamic memory allocation (implicitly or explicitly).  ... 
doi:10.1145/1669112.1669156 dblp:conf/micro/IsenJ09 fatcat:o562fjh2k5fnllebwrsvhkcwhq

POTRA

Ramon Bertran, Marc Gonzàlez, Xavier Martorell, Nacho Navarro, Eduard Ayguadé
2012 Proceedings of the 12th ACM SIGMETRICS/PERFORMANCE joint international conference on Measurement and Modeling of Computer Systems - SIGMETRICS '12  
Alternative methods are required to get power, temperature and performance estimates: for instance, the IBM POWER7 includes power models based on hardware counters collected on a per-core basis that are  ...  Besides, heuristics exclusively based on sensor distribution do not allow for predicting the effect on performance of any decision at the power management level.  ... 
doi:10.1145/2254756.2254827 dblp:conf/sigmetrics/BertranGMNA12 fatcat:5pelinzr4nbbnjhzx7wk6uwv5q

Adaptive GPU cache bypassing

Yingying Tian, Sooraj Puthoor, Joseph L. Greathouse, Bradford M. Beckmann, Daniel A. Jiménez
2015 Proceedings of the 8th Workshop on General Purpose Processing using GPUs - GPGPU 2015  
The technique is especially interesting for programs that do not use programmer-managed scratchpad memories.  ...  We propose a GPU cache management technique to improve the efficiency of small GPU caches while further reducing their power consumption.  ...  Comparison to Counter-Based Prediction Counter-based bypass prediction [27] is a CPU LLC bypassing technique.  ... 
doi:10.1145/2716282.2716283 dblp:conf/ppopp/TianPGBJ15 fatcat:dsin33y6zzeg7mwejrtiticoyq

Exploiting program hotspots and code sequentiality for instruction cache leakage management

J. S. Hu, A. Nadgir, N. Vijaykrishnan, M. J. Irwin, M. Kandemir
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
First, we adopt a hotspot detection mechanism by profiling the branch behavior at runtime and utilize this to implement a HotSpot based Leakage Management (HSLM) mechanism.  ...  We utilize the recently proposed drowsy cache that dynamically scales voltages for leakage reduction and implement various schemes that use different combinations of HSLM and JITA.  ...  In the schemes evaluated in this paper, we always use a periodic turn-off issued when the global counter expires in addition to the dynamic loop-based turnoff to account for the cases where the execution  ... 
doi:10.1145/871604.871606 fatcat:bxsvjiyqjfa6hkasbjbt7gwvdu

Exploiting program hotspots and code sequentiality for instruction cache leakage management

J. S. Hu, A. Nadgir, N. Vijaykrishnan, M. J. Irwin, M. Kandemir
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
First, we adopt a hotspot detection mechanism by profiling the branch behavior at runtime and utilize this to implement a HotSpot based Leakage Management (HSLM) mechanism.  ...  We utilize the recently proposed drowsy cache that dynamically scales voltages for leakage reduction and implement various schemes that use different combinations of HSLM and JITA.  ...  In the schemes evaluated in this paper, we always use a periodic turn-off issued when the global counter expires in addition to the dynamic loop-based turnoff to account for the cases where the execution  ... 
doi:10.1145/871506.871606 dblp:conf/islped/HuNVIK03 fatcat:7xvkweiiyfekfaluol3mah3usq

Three scalable approaches to improving many-core throughput for a given peak power budget

John Sartori, Rakesh Kumar
2009 2009 International Conference on High Performance Computing (HiPC)  
In this paper, we look at three scalable techniques for peak power management for many-core architectures.  ...  Recently proposed techniques for peak power management [18] involve centralized decisionmaking and assume quick evaluation of the various power management states.  ...  Reinitialization of the counter memory is performed periodically to allow for an unbiased evaluation of the processor power state even in the face of dynamically changing program behavior.  ... 
doi:10.1109/hipc.2009.5433221 dblp:conf/hipc/SartoriK09 fatcat:6z2axrme6rgy3j7naaquua3fku

A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design

Fayez Mohamood, Michael Healy, Sung Lim, Hsien-hsin Lee
2006 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
Based on the evaluation results using 2D floorplans, we show that our techniques can significantly improve inductive noise induced by current demand variation and reduce the average current variability  ...  With the trend of lower supply voltage and increased leakage power and current consumption, designing a processor for the worst case is becoming less appealing.  ...  To mitigate power consumption and its ensuing thermal management problems, aggressive power-saving techniques such as clocking gating and/or power gating were widely studied and applied.  ... 
doi:10.1109/micro.2006.5 dblp:conf/micro/MohamoodHLL06 fatcat:kz4zkqin2vahfiodyaul24mi2y

A Survey Of Power-Saving Techniques In Hpc

Pooja Pawar, Umesh Chavan
2016 Zenodo  
Based on this,discussion over the opportunities and problems present in the current techniques,We believe that this paper will help future researchers to explore more on this area.  ...  In recent years,increasing research efforts have also been devoted to the design of practical power saving techniques in HPC which is a integral part of content delivery networks (CDN)s.  ...  Authors combined dynamic bandwidth re-allocation (DBR) techniques with dynamic power management (DPM) techniques [11] and proposed a combined technique called Lock-Step (LS) for improving the performance  ... 
doi:10.5281/zenodo.1468712 fatcat:r53rne7ksbho5m2hjyywpte6m4

Using dynamic cache management techniques to reduce energy in a high-performance processor

Nikolaos Bellas, Ibrahim Hajj, Constantine Polychronopoulos
1999 Proceedings of the 1999 international symposium on Low power electronics and design - ISLPED '99  
In this work, we propose, implement, and evaluate a series of run-time techniques for dynamic analysis of the program instruction access behavior, which are then used to proactively guide the access of  ...  This mechanism can provide the instruction stream to the data path and, when managed properly, it can e ectively eliminate the need for high utilization of the more expensive I-Cache.  ...  The paper is organized as follows: in section 2, we review previous work regarding energy and power minimization in the microarchitectural level, as well as dynamic management of the memory hierarchy for  ... 
doi:10.1145/313817.313856 dblp:conf/islped/BellasHP99 fatcat:pnq4hnsnizgfbn4gw37o5c3cey

SAPA: Self-Aware Polymorphic Architecture [article]

Michel A. Kinsy, Mihailo Isakov, Alan Ehret, Donato Kava
2018 arXiv   pre-print
dynamic, autonomous resource management.  ...  Through the SAPA design, we examined the salient software-hardware features of adaptive computing systems that allow for (1) the dynamic allocation of computing resources depending on program needs (e.g  ...  dynamic, autonomous resource management.  ... 
arXiv:1802.05100v1 fatcat:txc5huhv2faqjmsawq55ujpfp4

Energy-efficient Algorithms for Ultrascale Systems

2015 Supercomputing Frontiers and Innovations  
first direction is concerned with power-aware and thermal-aware hardware design, including low-power techniques on all levels, i.e. the circuit and logic level, the processor, the memory and the interconnects  ...  The US DOE Exascale Initiative has set a target of 20 MW for the power consumption of an Exascale system.  ...  Power management techniques The Advanced Configuration and Power Interface (ACPI) [26] is an open standard for device power management co-developed by Hewlett-Packard, Intel, Microsoft, Phoenix, and  ... 
doi:10.14529/jsfi150205 fatcat:hceabokapvgozc4tsgikcjyq3u

Power-efficient and scalable load/store queue design via address compression

Yi-Ying Tsai, Chia-Jung Hsu, Chung-Ho Chen
2008 Proceedings of the 2008 ACM symposium on Applied computing - SAC '08  
This paper proposes an address compression technique for load/store queue (LSQ) to improve the scalability and power efficiency.  ...  A load/store queue (LSQ) typically needs a fullyassociative CAM structure to search the address for collision and consequently poses scalability challenges of power consumption and area cost.  ...  It's obvious that compression helps to reduce the CAM-based area of the LSQ, thus lower the dynamic power dissipation of the component.  ... 
doi:10.1145/1363686.1364042 dblp:conf/sac/TsaiHC08 fatcat:antwuo7mdvfbtmrbyrrq7h6wge
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