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The Open Channel

Patterson, Hennessy
1985 Computer  
Since MRSs have major impact on procedure calls, their importance can be artificially inflated by programs with unusual procedure call patterns.  ...  The RISC approach advocates a methodology that balances the needs of compilers with the implementation efficiency of the architecture.  ... 
doi:10.1109/mc.1985.1662752 fatcat:s32ueohchvacfhrbgnbxdktoti

Exploring Multi-core Design Space: Heracles vs. Rocket Chip Generator

Eduardo André Neves
2018 Journal of Computers  
It is the equivalent of Heracles for the MIPS architecture and, as such, provide several features that allows rapid development of RISC-V multi-core processors.  ...  RISC-V is a new instruction set architecture, developed at the University of California, Berkeley, that has several tools for designing architectures and processors that use this instruction set.  ...  This makes it possible to the developer to quickly measure the impact of each setting on system performance.  ... 
doi:10.17706/jcp.13.5.555-563 fatcat:i4km2rnotfcpbgd7eqci6o6d6a

Analysis on the Possibility of RISC-V Adoption

Ian Scott
2020 UC Merced Undergraduate Research Journal  
The authors of "Towards a High Performance RISC-V Emulator," Leandro Lupori, Vanderson Rosario, and Edson Borin claim that programs allowing efficient RISC-V emulation are unavailable [10] .  ...  In his thesis paper, "A Study on the Impact of Instruction Set Architectures on Processor's Performance," Ayaz Akram investigated how processors handle the execution of code in different ISAs [2] .  ... 
doi:10.5070/m4121046641 fatcat:pk6iq6ps35fpxosarz33dtm6ri

Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes

Li-Chun Lin, Shih-Hao Ou, Tay-Jyi Lin, Siang-Den Deng, Chih-Wei Liu
2007 2007 Asia and South Pacific Design Automation Conference  
The performance of single-issue RISC cores can be improved significantly with multi-issue architectures (i.e. superscalar or VLIW) by activating the parallel functional units concurrently.  ...  However, they suffer high complexity or huge code sizes. In this paper, we borrow some ideas from old vector machines and propose a novel DSP architecture with very compact codes.  ...  Instruction-set Architecture Design The ISA characterizes the processors and has large impact on the design effort and implementation complexity.  ... 
doi:10.1109/aspdac.2007.357965 dblp:conf/aspdac/LinOLDL07 fatcat:k6xsj6yydjdr3g3yheqyftlhju

Analyzing and modeling encryption overhead for sensor network nodes

Prasanth Ganesan, Ramnath Venugopalan, Pushkin Peddabachagari, Alexander Dean, Frank Mueller, Mihail Sichitiu
2003 Proceedings of the 2nd ACM international conference on Wireless sensor networks and applications - WSNA '03  
The objective of this work is to cover a wide class of commonly used encryption algorithms and to determine the impact of embedded architectures on their performance.  ...  Experimental measurements indicate uniform cryptographic cost for each encryption class and each architecture class and negligible impact of caches.  ...  It is ARM architecture v.5TE compliant and a successor to the StrongARM processor. It is based on Intel's superpipelined RISC technology. The PXA250 has 32 KB of instruction and data caches.  ... 
doi:10.1145/941370.941372 fatcat:oiubu526lvhtxp6mi72kerujim

Analyzing and modeling encryption overhead for sensor network nodes

Prasanth Ganesan, Ramnath Venugopalan, Pushkin Peddabachagari, Alexander Dean, Frank Mueller, Mihail Sichitiu
2003 Proceedings of the 2nd ACM international conference on Wireless sensor networks and applications - WSNA '03  
The objective of this work is to cover a wide class of commonly used encryption algorithms and to determine the impact of embedded architectures on their performance.  ...  Experimental measurements indicate uniform cryptographic cost for each encryption class and each architecture class and negligible impact of caches.  ...  It is ARM architecture v.5TE compliant and a successor to the StrongARM processor. It is based on Intel's superpipelined RISC technology. The PXA250 has 32 KB of instruction and data caches.  ... 
doi:10.1145/941350.941372 dblp:conf/wsna/GanesanVPDMS03 fatcat:wz2vtzx2zrglvkarbtqolpa4ae

Encryption overhead in embedded systems and sensor network nodes

Ramnath Venugopalan, Prasanth Ganesan, Pushkin Peddabachagari, Alexander Dean, Frank Mueller, Mihail Sichitiu
2003 Proceedings of the international conference on Compilers, architectures and synthesis for embedded systems - CASES '03  
The objective of this work is to cover a wide class of commonly used encryption algorithms and to determine the impact of embedded architectures on their performance.  ...  Experimental measurements indicate uniform cryptographic cost for each encryption class and each architecture class and negligible impact of caches.  ...  It is ARM architecture v.5TE compliant and a successor to the StrongARM processor. It is based on Intel's superpipelined RISC technology. The PXA250 has 32 KB of instruction and data caches.  ... 
doi:10.1145/951710.951737 dblp:conf/cases/VenugopalanGPDMS03 fatcat:fncmkibsebfbtaa5z36cto7mba

A Survey on RISC-V Security: Hardware and Architecture [article]

Tao Lu
2021 arXiv   pre-print
This paper summarizes the representative security mechanisms of RISC-V hardware and architecture. Based on our survey, we predict the future research and development directions of RISC-V security.  ...  For decades, these processors were mainly based on the Arm instruction set architecture (ISA).  ...  Then, they implement preliminary hardware mitigation measures against this type of attack, prove its effectiveness, and measure its impact on performance and area size.  ... 
arXiv:2107.04175v1 fatcat:hr6avyprj5dvpav2pvnmfmvg2a

Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures

E. Blem, J. Menon, K. Sankaralingam
2013 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)  
Further, the traditionally low-power ARM ISA is entering the high-performance server market, while the traditionally high-performance x86 ISA is entering the mobile low-power device market.  ...  We find that ARM and x86 processors are simply engineering design points optimized for different levels of performance, and there is nothing fundamentally more energy efficient in one ISA class or the  ...  Thanks to Doug Burger, Mark Hill, Guri Sohi, David Wood, Mike Swift, Greg Wright, Jichuan Chang, and Brad Beckmann for comments on the paper and thought-provoking discussions on ISA impact.  ... 
doi:10.1109/hpca.2013.6522302 dblp:conf/hpca/BlemMS13 fatcat:axsmoctvajbkrikjkidm4dhrby

How much do your coopetitors' capabilities matter in the face of technological change?

Allan Afuah
2000 Strategic Management Journal  
This paper explores the effects on a firm of the impact of a technological change on its co-opetitors.  ...  It uses detailed data on the adoption of RISC (Reduced Instruction Set Computer) technology by computer workstation makers to demonstrate the need to view resources as residing in a network and not in  ...  ACKNOWLEDGEMENTS I would like to thank Rebecca Henderson, Will Mitchell, Dick Schmalensee, Jim Utterback, the editors of the special issue of SMJ on Strategic Networks, and two anonymous referees for useful  ... 
doi:10.1002/(sici)1097-0266(200003)21:3<397::aid-smj88>3.3.co;2-t fatcat:d3vapabnd5eprds4aze7axr5m4

How much do yourco-opetitors' capabilities matter in the face of technological change?

Allan Afuah
2000 Strategic Management Journal  
This paper explores the effects on a firm of the impact of a technological change on its co-opetitors.  ...  It uses detailed data on the adoption of RISC (Reduced Instruction Set Computer) technology by computer workstation makers to demonstrate the need to view resources as residing in a network and not in  ...  ACKNOWLEDGEMENTS I would like to thank Rebecca Henderson, Will Mitchell, Dick Schmalensee, Jim Utterback, the editors of the special issue of SMJ on Strategic Networks, and two anonymous referees for useful  ... 
doi:10.1002/(sici)1097-0266(200003)21:3<397::aid-smj88>3.0.co;2-1 fatcat:7j5dtvt6knd2bmpnjb6ee3m3ky

Giving applications access to Gb/s networking

J.M. Smith, C.B.S. Traw
1993 IEEE Network  
these tradeoffs on applications performance.  ...  In this paper, we outline a variety of approaches to the architecture of such systems, examine several design points, and study one example in detail.  ...  Memory impact was studied on the same RISC System/6000 Model 580 using a program we designed which measures the performance of the main memory subsystem.  ... 
doi:10.1109/65.224055 fatcat:2szgte52brhyzbgrd3ipcwfts4

The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology [article]

Florian Zaruba, Luca Benini
2019 arXiv   pre-print
Our main contribution in this work is a thorough power, performance, and efficiency analysis of the RISC-V ISA targeting baseline "application class" functionality, i.e. supporting the Linux OS and its  ...  Our analysis is based on a detailed power and efficiency analysis of the RISC-V ISA extracted from silicon measurements and calibrated simulation of an Ariane instance (RV64IMC) taped-out in GlobalFoundries  ...  This work has received funding from the European Unions Horizon 2020 research and innovation program under grant agreement No 732631, project "OPRECOMP".  ... 
arXiv:1904.05442v1 fatcat:qawowriv7zawxio4ayy76lngfe

Didactic architectures and simulator for network processor learning

Henrique Cota de Freitas, Carlos Augusto P. S. Martins
2003 Proceedings of the 2003 workshop on Computer architecture education Held in conjunction with the 30th International Symposium on Computer Architecture - WCAE '03  
A Network Processor can use one RISC processor and coprocessors like the packet processors, or only multiple RISC processors.  ...  There are four important results: Reconfigurable CISC Network Processor (RCNP) architecture, Reconfigurable RISC Network Processor (R2NP) architecture, Network Processor Simulator (NPSIM), and a performance  ...  ) [21] , simulate it in a real network system [2, 28] , and to develop didactic environment to learn Network Processors.  ... 
doi:10.1145/1275521.1275540 dblp:conf/wcae/FreitasM03 fatcat:j2arrrt35nghhallqritzghefi

Reduced instruction set computers

David A. Patterson
1985 Communications of the ACM  
Reduced instruction set computers aim for both simplicity in hardware and synergy between architectures and compilers.  ...  Optimizing compilers are used to compile programming languages down to instructions that are as unencumbered as microinstructions in a large virtual address space, and to make the instruction cycle time  ...  design effort while maximizing the cost/performance factor.  ... 
doi:10.1145/2465.214917 fatcat:63bzmslqwvbgdbblr2qcxvo45y
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