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Product On-Chip Process Compensation for Low Power and Yield Enhancement [chapter]

Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azemard, Vincent Dumettier, Abhishek Bansal, Sebastien Barasinski, Alain Tournier, Guy Durieu, David Meyer, Pierre Busson, Sarah Verhaeren (+1 others)
2010 Lecture Notes in Computer Science  
This paper aims at introducing a reliable on-chip process compensation flow for industrial integrated systems.  ...  The proposed design flow includes efficient methodologies to gather/sort on-chip process data but also post-silicon tuning strategies and validation methods at both design and test steps.  ...  Discussions and Perspectives In addition to a significant power reduction on fast circuits, the integration of on-chip sensors may enhance the production quality.  ... 
doi:10.1007/978-3-642-11802-9_29 fatcat:vqj74wa7sfd3rpbcerglctj334

Architecture Considerations for Multi-Format Programmable Video Processors

Jonah Probell
2007 Journal of Signal Processing Systems  
Because low-cost memory architectures are not optimized for the random access patterns of video processing, the performance of video processors is often limited by memory bandwidth rather than processing  ...  When choosing a video processor it is important to consider many factors, particularly performance, cost, power consumption, programmability, and peripheral support.  ...  For battery powered systems, such as mobile phones, portable media players, and camcorders, low energy consumption is critical to product success.  ... 
doi:10.1007/s11265-007-0116-z fatcat:vdmeywccjjf3vgpmn53s6ogemq

Survey of Robustness Enhancement Techniques for Wireless Systems-on-a-Chip and Study of Temperature as Observable for Process Variations

Marvin Onabajo, Didac Gómez, Eduardo Aldrete-Vidrio, Josep Altet, Diego Mateo, Jose Silva-Martinez
2011 Journal of electronic testing  
This paper contains an overview of contemporary self-test and performance enhancement strategies for single-chip transceivers.  ...  Built-in test and on-chip calibration features are becoming essential for reliable wireless connectivity of next generation devices suffering from increasing process variations in CMOS technologies.  ...  Acknowledgment This work was supported in part by grants from TAMU-CONACYT, the National Science Foundation under contract ECCS-0824031, as well as project ENIAC MODERN (Spanish MICINN PLE2009-0024) and  ... 
doi:10.1007/s10836-011-5199-6 fatcat:ppakxglcdndb3hpldruv4bwj5m

A low noise, high PSR low-dropout regulator for low-cost portable electronics

Karim El Khadiri, Hassan Qjidaa
2013 2013 ACS International Conference on Computer Systems and Applications (AICCSA)  
This paper presents A low noise, high PSRR lowdropout regulator for low-cost portable electronics.  ...  load regulation of better than 0.25% and a low quiescent current of only 90uA and ultra-low noise of only 65 nV/SqrtHz.  ...  A low drop out regulator in standard CMOS process, with new dynamic compensation, low-noise, high openloop gain, and high-PSRR is introduced in this article.  ... 
doi:10.1109/aiccsa.2013.6616415 dblp:conf/aiccsa/KhadiriQ13 fatcat:6hdih5po3bfbfdpe5nlpzxinei

A Linearity-Enhanced Time-Domain CMOS Thermostat with Process-Variation Calibration

Chun-Chi Chen, Yi Lin
2014 Sensors  
To enhance the on-chip linearity, this study proposes a novel temperature-sensing cell comprising a simple buffer and a buffer with a thermal-compensation circuit to achieve a linearised delay.  ...  To achieve one-point calibration support, an adjustable-gain time stretcher and calibration circuit were adopted for the process-variation calibration.  ...  The authors would like to thank the Chip Implementation Center (CIC) for support of EDA tools and chip implementation.  ... 
doi:10.3390/s141018784 pmid:25310469 pmcid:PMC4239910 fatcat:camu7lbgsfh2nbl3c4r2wp7fba

2001 technology roadmap for semiconductors

A. Allan, D. Edenfeld, W.H. Joyner, A.B. Kahng, M. Rodgers, Y. Zorian
2002 Computer  
Acknowledgments We acknowledge the efforts of the many individuals who contributed to making the 2001 edition of The International Technology Roadmap for Semiconductors a successful endeavor.  ...  Error-correction for single-event upset in logic will increase, as will using redundancy and reconfigurability to compensate for yield loss.  ...  enhancement, and increased vulnerability to atomic-scale process variability, severely threatens parametric yield (dollar per wafer after bin-sorting).  ... 
doi:10.1109/2.976918 fatcat:mv3q7f3l2zfjng2i5rvipkdhsi

VaROT: Methodology for Variation-Tolerant DSP Hardware Design Using Post-Silicon Truncation of Operand Width

K Kunaparaju, S Narasimhan, S Bhunia
2011 2011 24th Internatioal Conference on VLSI Design  
Process Variation Tolerant Low Power DCT Architecture An other process variation tolerant low power design for DCT architecture has been proposed in [9] .  ...  Low performance chips need to discarded which in turn effects the yield and hence the cost.  ...  IMPLEMENTATION OF VAROT ON FIR In this chapter we present the implementation of the proposed methodology on Finite Impulse Response(FIR).  ... 
doi:10.1109/vlsid.2011.58 dblp:conf/vlsid/KunaparajuNB11 fatcat:lyjvho7l7zct7fd36gfucaztzy


Ashvani Kumar Mishra, Rishikesh Pandey
Low Drop-Out Regulators showed advantage over its counterpart. The design of Low Drop-Out Regulators with high performance and less Die area is challenging problem now-a-days.  ...  The advancement in battery operated portable devices, noise sensitive devices and other devices, which need high precision supply voltages has fuelled the growth of Low Drop-Out Regulators.  ...  But for portable applications there are many LDOs which utilize on-chip capacitor with different specific schemes for compensation.  ... 
doi:10.24297/ijct.v4i2a2.3179 fatcat:g4zjhgtbcbggfakbvnw7ekqwtu

All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement

Chun-Chi Chen, Chao-Lieh Chen, Yi Lin
2016 Sensors  
Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output.  ...  With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time.  ...  Yi Lin implemented the circuit on FPGA chips and tested the chips. Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/s16020176 pmid:26840316 pmcid:PMC4801553 fatcat:zm3eltmzsfb3zevcbkxbes6dwe

Using test data to improve IC quality and yield

Anne Gattiker
2008 2008 IEEE/ACM International Conference on Computer-Aided Design  
Product-impact-oriented test-based learning provides insight into the nature of model-hardware mismatches and variability that exist on and impact real products.  ...  The complexity of interactions in today's manufacturing processes makes test structures and experiments inadequate as sole drivers of yield-learning and design-formanufacturing [DfM].  ...  ACKNOWLEDGMENTS The author deeply appreciates the contributions of many other individuals in IBM Research and IBM Systems & Technology Group for the design, manufacturing and measurements utilized in this  ... 
doi:10.1109/iccad.2008.4681663 dblp:conf/iccad/Gattiker08 fatcat:ah7seqxsjrgdvbxuhd5pk5osoy

Through the Looking Glass?Part 2 of 2: Trend Tracking for ISSCC 2013 [ISSCC Trends]

Kenneth C. Smith, Alice Wang, Laura C. Fujino
2013 IEEE Solid-State Circuits Magazine  
This will yield solutions with lower cost and lower cooling demands, resulting in greener products for the future.  ...  Redundancy and ECC protection are also keys to ensure yield and reliability when embedded SRAM products go into production.  ...  been largely a team effort by several members of each subcommittee, each has operated under the direction of his or her subcommittee chair, as follows: Get to Know Technical Standards The foundation for  ... 
doi:10.1109/mssc.2013.2254632 fatcat:ryhipjjwdbev7ptair2nizyh7y

Industrial evaluation of transition fault testing for cost effective offline adaptive voltage scaling

Mahroo Zandrahimi, Philippe Debaud, Armand Castillejo, Zaid Al-Ars
2018 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
Adaptive voltage scaling (AVS) has been used widely to compensate for process, voltage, and temperature variations as well as power optimization of integrated circuits.  ...  , and a low accuracy that results in extra margins, which consequently lead to yield loss and performance limitations.  ...  Conversion from Vmin to Fmax might be required depending on either performance estimation is done for yield enhancement or power optimization.  ... 
doi:10.23919/date.2018.8342022 dblp:conf/date/ZandrahimiDCA18 fatcat:bkr3fof2nvgxldsddi3ufpsbyy

Design techniques for variability mitigation

Shady Agwa, Eslam Yahya, Yehea Ismail
2013 International Journal of Circuits and Architecture Design  
Delay and power consumption of the manufactured chips deviate from their predesigned values due to process, voltage and temperature (PVT) variations.  ...  As the fabrication technology migrated towards the nanometre scale, 22 nm and beyond, yield enhancement has become one of the challenges facing the integrated circuits design community.  ...  Acknowledgements This research was partially funded by Zewail City of Science and Technology, AUC, the STDF, Intel, Mentor Graphics, and MCIT.  ... 
doi:10.1504/ijcad.2013.057450 fatcat:uxft2eddjrg7zizwowqjotv7s4

A monolithically integrated detector-preamplifier on high-resistivity silicon

S. Holland, H. Spieler
1990 IEEE Transactions on Nuclear Science  
Measurements with an Am 241 radiation source yield an equivalent input noise charge of 800 electrons at 200 ns shap ing time for a 1.4 mm 2 detector with on-chip amplifier in an experimental setup with  ...  The amplifier is internally compensated and toe measured gain-bandwidth product is 30 MHz with an input-referred noise of IS nV/VHz in the while noise regime.  ...  Hence the open-loop measure ments yield a gain-bandwidth product and input-referred noise acceptable for applications using low-capacitance detectors.  ... 
doi:10.1109/23.106663 fatcat:3fh4s4hpibaujncysq7kzarioq

An Image Processing Pipeline with Digital Compensation of Low Cost Optics for Mobile Telephony

Nikolaos Bellas, Arnold Yanof
2006 2006 IEEE International Conference on Multimedia and Expo  
In this paper, we describe the algorithms and the hardware implementation of a novel color processing chain that uses image processing techniques to compensate for the spatial variations in image attributes  ...  and quality due to low cost optics.  ...  For example, when the imaging system operates in single capture mode, the chip and the sensor can be placed into a low power state by clock gating the flip flops.  ... 
doi:10.1109/icme.2006.262764 dblp:conf/icmcs/BellasY06 fatcat:utkytc7r55hjzaworja4qri47i
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