A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Filters
Processor-memory interconnections for multiprocessors
1979
Proceedings of the 6th annual symposium on Computer architecture - ISCA '79
Preserved Fulltext
A new class of interconnection networks is proposed for processor to memory communication in multiprocessing systems. These networks allow a direct link between any processor to any memory module. ...
There is considerable research on the permutation networks for parallel (SIMD) processors but almost no research on processor-memory interconnections requiring random access capabilities. ...
The principle characteristics of a multiprocessor system is the ability of each processor to share a single main memory. ...
doi:10.1145/800090.802906
dblp:conf/isca/Patel79
fatcat:ub2emugphrhntjbpdzviztlify
Performance of Processor-Memory Interconnections for Multiprocessors
1981
IEEE transactions on computers
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
A new class of interconnection networks is proposed for processor to memory communication in multiprocessing systems. These networks allow a direct link between any processor to any memory module. ...
There is considerable research on the permutation networks for parallel (SIMD) processors but almost no research on processor-memory interconnections requiring random access capabilities. ...
The principle characteristics of a multiprocessor system is the ability of each processor to share a single main memory. ...
doi:10.1109/tc.1981.1675695
fatcat:mdxmpmrtbzeqbpd3gqswh3tgvq
Application Specific Customization and Scalability of Soft Multiprocessors
2009
2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
Average memory usage per processor for eight benchmarks.................. Total memory usage of scaling soft multiprocessor systems .................. ...
We use M4K and BRAM memory bits to implement instruction and data memories for the processors. ...
doi:10.1109/fccm.2009.41
dblp:conf/fccm/UnnikrishnanZT09
fatcat:7cjy7ltl4rcyzlo7e2p4hdecdq
Multiprocessor Organization---a Survey
1977
ACM Computing Surveys
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2006; you can also visit the original URL.
The file type is application/pdf.
Three organizations for multiprocessor operating systems are also discussed: 1) master-slave; 2) separate executive for each processor; and 3) symmetric treatment of all processors. ...
It is possible to characterize the hardware organization by the nature of the system utilized to interconnect the primary functional units--processors, memory, and input/output channels. ...
Contention for a processor bus Contention for the shared memory bus Contention for the shared memories Contention for a single system-wide software resource, assuming each processor wants the resource ...
doi:10.1145/356683.356688
fatcat:fny4nvyqtfghxp2eydacbiogg4
Performance Evolution of Efficient Cluster Based Multiprocessor Systems with Analytical Model
2020
International Journal of Research in Advent Technology
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
There are some effective existing interconnection networks playing vital role in managing nodes in individual cluster and interconnection between clusters. ...
The multiprocessor system alone could not satisfy all the present system complexities. These problems can be minimized with Cluster based Multiprocessor system. ...
Failure either memory module bus or interconnection network leads total failure in the system. This is one of the reasons for poor reliability in cluster-based multiprocessor system. ...
doi:10.32622/ijrat.81202015
fatcat:3ecbyvxqgzdahfgbhbcel7i3kq
Development of Cluster-based Multiprocessor Systems with Analytical Model: A Approach
2019
Journal of Communications
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
There are some effective existing interconnection networks playing vital role in managing nodes in individual cluster and interconnection between clusters. ...
The multiprocessor system alone could not satisfy all the present system complexities. These problems can be minimized with Cluster based Multiprocessor system. ...
In the entire multiprocessor cluster based system individual cache memory modules are maintained to store a copy of main memory block. This is done for faster accessing of data at processors. ...
doi:10.12720/jcm.14.11.1091-1097
fatcat:l2bgohfgefhjbg6tqxjosx3xvm
Criticality Aware Multiprocessors
[article]
2016
arXiv
pre-print
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
Typically, a memory request from a processor may need to go through many intermediate interconnect routers, directory node, owner node, etc before it is finally serviced. ...
Criticality aware multiprocessor provides a new direction for tapping performance in a shared memory multiprocessor and can provide substantial speedup in lock intensive benchmarks. ...
Overview Typically, a memory request from a processor may need to go through many intermediate interconnect routers, directory node, owner node, etc before it is finally serviced. ...
arXiv:1606.05933v1
fatcat:wfs2cigl75ezddzv5mfnbhxzeu
Shared Memory Multiprocessors
[chapter]
2004
Parallel Computing on Heterogeneous Networks
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2015; you can also visit the original URL.
The file type is application/pdf.
The goal of this report in to give an overview of issues and tradeoffs involved in memory hierarchy design for shared memory multiprocessors. ...
In this memory system organisation, every processor (or node consisting of more than one processors) has it own private main memory and can access remote memory connected to other nodes through interconnection ...
doi:10.1002/0471654167.ch3
fatcat:dvaj7kmetfgr7bkmdrmvzljwda
Reducing run queue contention in shared memory multiprocessors
1997
Computer
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Feature No single method for mitigating the performance problems of centralized and distributed run queues is entirely successful. ...
I am grateful for the financial support of Carleton University and the Natural Sciences and Engineering Research Council of Canada. ...
In UMA multiprocessors, the cost of accessing a memory location is the same for any processor in the system. In NUMA multiprocessors, memory access cost varies. ...
doi:10.1109/2.573673
fatcat:42npmhig3ffqxpdnvqhtakwsl4
Predicting the performance measures of an optical distributed shared memory multiprocessor by using support vector regression
2010
Expert systems with applications
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2015; you can also visit the original URL.
The file type is application/pdf.
Recent advances in the development of optical technologies suggest the possible emergence of optical interconnects within distributed shared memory (DSM) multiprocessors. ...
of a DSM multiprocessor architecture interconnected by the Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus), which is a high-bandwidth, fiber-optic interconnection network. ...
The interconnection network has a direct effect on the remote memory latency, which is caused by accessing a memory location in a processor other than the one originating the request. ...
doi:10.1016/j.eswa.2010.02.092
fatcat:in5a76fxgjb7xcbykg5hkkzdva
A first glance at Kilo-instruction based multiprocessors
2004
Proceedings of the first conference on computing frontiers on Computing frontiers - CF'04
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2006; you can also visit the original URL.
The file type is application/pdf.
In this paper, we will study for the first time, the influence of Kilo-instruction processors on the performance of small-scale CC-NUMA multiprocessors. ...
In short, our results show dramatic performance gains over multiprocessors based on current microprocessors and dictate a possible way to build future shared-memory multiprocessor systems. ...
RSIM Processor Microarchitecture
Interconnection Network Models In the multiprocessor design arena the Memory Wall reveals as an exacerbated problem. ...
doi:10.1145/977091.977120
dblp:conf/cf/GalluzziPCBGV04
fatcat:whrryqvb6vcd7hu2lu5nm7fhuy
Performance of multiprocessor interconnection networks
1989
Computer
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2007; you can also visit the original URL.
The file type is application/pdf.
The main difference between them lies in the level at which interactions between the processors occur. A multiprocessor must permit all processors to directly share the main memory. ...
A processor cannot directly access another processor's local memory. Multiprocessors can be further divided as tightlycoupled and loosely coupled. ...
An IN is a complex connection of
Figure 6 . 6 A classification of multiprocessor interconnection networks.
Figure 7 . 7 A queueing model for asynchronous crossbar multiprocessors. ...
doi:10.1109/2.19830
fatcat:5fp6yvp5frc4tg5f3aaz4v5ake
CDMA as a multiprocessor interconnect strategy
2001
Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2008; you can also visit the original URL.
The file type is application/pdf.
A binary CDMA bus is proposed as a communications interconnect for multiprocessor systems. ...
Mean value analysis is used to show that, for resource bandwidth-limited applications, the binary CDMA bus can deliver a throughput speedup over a split-transaction bus as large numbers of processors are ...
The performance of a shared-memory multiprocessor system often depends on the characteristics of the bus interconnect used to share data among the processors and memory modules in the system [1] [2] . ...
doi:10.1109/acssc.2001.987690
fatcat:kmrdma63nrbo7nyvkmtzqx5ixu
Evaluating kilo-instruction multiprocessors
2004
Proceedings of the 3rd workshop on Memory performance issues in conjunction with the 31st international symposium on computer architecture - WMPI '04
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2005; you can also visit the original URL.
The file type is application/pdf.
What we propose, in this paper, is the use of Kilo-instruction processors as computing nodes for small-scale CC-NUMA multiprocessors. ...
Current multiprocessor systems also have to deal with this increasing memory latency while facing other sources of latencies: those coming from communication among processors. ...
These directions include new multiprocessor models and new interconnection networks. ...
doi:10.1145/1054943.1054953
dblp:conf/wmpi/GalluzziBPGCV04
fatcat:2r3xxn2qy5b4ppazmw5pc54wnm
Reconfigurable interconnection networks in Distributed Shared Memory systems: a study on communication patterns
2006
2006 First International Conference on Communications and Electronics
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2007; you can also visit the original URL.
The file type is application/pdf.
The static interconnection network topologies in the distributed shared memory systems (DSM) have several limitations. ...
The reconfigurable interconnection networks may reduce the network congestion, network latency and improve the overall performance. ...
Bui Viet Khoi gratefully acknowledges the receipt of a grant from the Flemish Interuniversity Council for University Development Cooperation (VLIR UOS) which enabled the research team to carry out this ...
doi:10.1109/cce.2006.350798
fatcat:swey7l64j5gqbgwxqsvmlq5yc4
« Previous
Showing results 1 — 15 out of 11,913 results