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A Generic Architecture for Integrated Smart Transducers [chapter]

Martin Delvai, Ulrike Eisenmann, Wilfried Elmenreich
2003 Lecture Notes in Computer Science  
Due to the fact that all processor cores are code compatible, programs developed for one node run on all other nodes without any modification.  ...  Our approach offers the possibility to design different smart transducer nodes as a system-on-a-chip within the same platform.  ...  We would like to thank our colleague Stefan Pitzek and Christian Trödhandl for fruitful comments for improving the paper.  ... 
doi:10.1007/978-3-540-45234-8_71 fatcat:yxrz25ctfzcyhoqjwb2pgqqeeq

An Automated Mapping of Timed Functional Specification to a Precision Timed Architecture

Shanna-Shaye Forbes, Hiren D. Patel, Edward A. Lee, Hugo A. Andrade
2008 2008 12th IEEE/ACM International Symposium on Distributed Simulation and Real-Time Applications  
LabVIEW is one example of a graphical programming language that supports timing specifications in the form of timed-loops.  ...  We demonstrate the use of the plug-in with a simple producer/consumer example that uses timing to enforce synchronization.  ...  Acknowledgements This work was supported in part by the Center for Hybrid and Embedded Software Systems (CHESS) at UC Berkeley, which receives support from the National Science  ... 
doi:10.1109/ds-rt.2008.45 dblp:conf/dsrt/ForbesPLA08 fatcat:rpu7azpteffrldczbpphwru6lm

FlexPRET: A processor platform for mixed-criticality systems

Michael Zimmer, David Broman, Chris Shaver, Edward A. Lee
2014 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)  
We present FlexPRET, a processor designed specifically for mixed-criticality systems by allowing each task to make a trade-off between hardware-based isolation and efficient processor utilization.  ...  Highcriticality tasks require spatial and temporal isolation guarantees, whereas low-criticality tasks should efficiently utilize hardware resources.  ...  Acknowledgement This work was supported in part by the Center for Hybrid and Embedded Software Systems (CHESS) at UC Berkeley, which receives support from the National Science Foundation (NSF awards #0720882  ... 
doi:10.1109/rtas.2014.6925994 dblp:conf/rtas/ZimmerBSL14 fatcat:ew6tiptqnzbtln7zvznfuskj34

Patmos: a time-predictable microprocessor

Martin Schoeberl, Wolfgang Puffitsch, Stefan Hepp, Benedikt Huber, Daniel Prokesch
2018 Real-time systems  
This abstraction further increases the WCET bound. This paper presents a way out of this dilemma: a processor designed for real-time systems.  ...  We design and optimize a processor, called Patmos, for low WCET bounds rather than for high average-case performance. Patmos is a dual-issue, statically scheduled RISC processor.  ...  Acknowledgements We would like to thank Tommy Thorn for the ongoing discussions on computer architecture, processor design, and optimization for an FPGA implementation.  ... 
doi:10.1007/s11241-018-9300-4 fatcat:werexvn555bz5mhw7o2fia2abu

A time-predictable execution mode for superscalar pipelines with instruction prescheduling

Christine Rochange, Pascal Sainrat
2005 Proceedings of the 2nd conference on Computing frontiers - CF '05  
The time predictability of the components of a real-time system is required whenever it must be guaranteed that deadlines will be met.  ...  We acknowledge the difficulty of taking into account more and more dynamic mechanisms within static analysis and this motivates our approach that consists in making the processor fit WCET estimation techniques  ...  We feel that the model presented in [17] might miss this kind of effect. Delvai et al. [7] described the SPEAR processor that supports the single-path programming paradigm.  ... 
doi:10.1145/1062261.1062312 dblp:conf/cf/RochangeS05 fatcat:jqay5l4xybekfdmzv2elwk6j4y

An Operating System for a Time-Predictable Computing Node [chapter]

Guenter Khyo, Peter Puschner, Martin Delvai
2008 Lecture Notes in Computer Science  
The increasing complexity of speed-up mechanisms found in modern computer architectures makes it difficult to predict the timing of the software that runs on this hardware, especially when the software  ...  We explain the principles and mechanisms we use to achieve this predictability and show the results of an experiment that demonstrates the feasibility of our concepts.  ...  Temporal Characteristics For the real-time application designer and the planning tool, knowledge of the execution times of the core components of the OS is essential.  ... 
doi:10.1007/978-3-540-87785-1_14 fatcat:7lytvqdnxrb37afbl3pekd6npi

JOP: A Java Optimized Processor [chapter]

Martin Schoeberl
2003 Lecture Notes in Computer Science  
This paper describes the architecture of JOP and proposes a simple real-time extension of Java for JOP.  ...  Java is still not a common language for embedded systems.  ...  Further research will focus on the predictable instruction cache and hardware support for the real-time extensions of Java.  ... 
doi:10.1007/978-3-540-39962-9_43 fatcat:lpjkz4prfbgxngd7ctgv5446qq

Predictable programming on a precision timed architecture

Ben Lickly, Isaac Liu, Sungjun Kim, Hiren D. Patel, Stephen A. Edwards, Edward A. Lee
2008 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems - CASES '08  
We demonstrate the effectiveness of this precision-timed (PRET) architecture through example applications running in simulation.  ...  Modern processors go to extreme lengths to ensure their function is predictable, but have abandoned predictable timing in favor of average-case performance.  ...  ACKNOWLEDGMENTS This work was supported in part by the Center for Hybrid and Embedded Software Systems (CHESS) at UC Berkeley, which receives support from the National Science Foundation (NSF award #CCR  ... 
doi:10.1145/1450095.1450117 dblp:conf/cases/LicklyLKPEL08 fatcat:gyauzga25rh47l5hk77ob653ha

Time-Predictable Computer Architecture

Martin Schoeberl
2009 EURASIP Journal on Embedded Systems  
The proposed architecture is evaluated with implementation of some features in a Java processor. The resulting processor is a good target for WCET analysis and still performs well in the average case.  ...  In this paper, we evaluate the issues of current architectures with respect to WCET analysis. Then, we propose solutions for a time-predictable computer architecture.  ...  Acknowledgment The author thanks Wolfgang Puffitsch and Florian Brandner for the productive discussions on the topic and suggestions for improving the paper.  ... 
doi:10.1155/2009/758480 fatcat:4mxu4useyngezo5busxvnx3ize

UNICOR: a species connectivity and corridor network simulator

E. L. Landguth, B. K. Hand, J. Glassy, S. A. Cushman, M. A. Sawaya
2012 Ecography  
Outputs can be used to designate movement corridors, identify isolated populations, and prioritize conservation plans to promote species persistence.  ...  Acknowledgements -We are grateful to Ross Carlson for maintaining the website, debugging, and graphics support.  ...  We thank Whisper Camel and the Confederated Salish and Kootenay Tribes and Marcel Huijser from the Western Transportation Inst. at Montana State Univ. for providing GIS data for Highway 93.  ... 
doi:10.1111/j.1600-0587.2011.07149.x fatcat:3s2kcabhdvap7dxmqw7curpmri

Objective speech intelligibility measurement for cochlear implant users in complex listening environments

João F. Santos, Stefano Cosentino, Oldooz Hazrati, Philipos C. Loizou, Tiago H. Falk
2013 Speech Communication  
To date, existing objective measures have focused on normal hearing model, and limited use has been found for restorative hearing instruments such as cochlear implants (CIs).  ...  Experimental results show that the proposed CI-inspired objective measures outperformed all existing measures; gains by as much as 22% could be achieved in rank correlation.  ...  Acknowledgments THF and JFS thank the Natural Sciences and Engineering Research Council of Canada for their financial support. SC acknowledges funding from UCL and Neurelec.  ... 
doi:10.1016/j.specom.2013.04.001 pmid:23956478 pmcid:PMC3744246 fatcat:ttzqjv4gyva65f5v3glvkxty6y

Ærø: A Platform Architecture for Mixed-Criticality Airborne Systems

Shibarchi Majumder, Jens F Dalsgaard Nielsen, Thomas Bak
2019 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
All the components are designed with non-blocking sequential logic for easy timing analysis and to support fast clocking.  ...  any software support for virtualization.  ...  For more than 15 years he has been heading the student satellite activities at Aalborg University which has launched 5 cubesats 100% developed at AAU and participated in three other launches.  ... 
doi:10.1109/tcad.2019.2960359 fatcat:aomafzonkfb7jhbmfqy5ggfivu

Changes in Pitch with a Cochlear Implant Over Time

Lina A. J. Reiss, Christopher W. Turner, Sheryl R. Erenberg, Bruce J. Gantz
2007 Journal of the Association for Research in Otolaryngology  
We also found that the early pitch sensations for a constant electrode location can vary greatly across subjects and that these variations are strongly correlated with speech reception performance.  ...  In the normal auditory system, the perceived pitch of a tone is closely linked to the cochlear place of vibration.  ...  We also thank Paul Abbas, Steven Green, Robert Hong, and the Iowa Auditory Journal Group for comments on the manuscript.  ... 
doi:10.1007/s10162-007-0077-8 pmid:17347777 pmcid:PMC2538353 fatcat:wt2wj7k5y5cxtdmojvrz5ni3gi

Reliability: Fallacy or Reality?

Antonio Gonzalez, Scott Mahlke, Shubu Mukherjee, Resit Sendag, Derek Chiou, Joshua J. Yi
2007 IEEE Micro  
Although Mahlke argues the fallacy viewpoint in this article, his research group actively works in the areas of designing reliable and adaptive computer systems.  ...  Neither author represents the position of Intel Corporation in any shape or form.  ...  The SPEARS Group spearheads architectural innovation in the delivery of microprocessors and chipsets by building and supporting simulation and analytical models of performance, power, and reliability.  ... 
doi:10.1109/mm.2007.107 fatcat:z3nkucclerednjg445p77c6lci

Parallel unstructured tetrahedral mesh adaptation: algorithms, implementation and scalability

P. M. Selwood, M. Berzins
1999 Concurrency Practice and Experience  
The use of unstructured adaptive tetrahedral meshes in the solution of transient flows poses a challenge for parallel computing due to the irregular and frequently changing nature of the data and its distribution  ...  A parallel mesh adaptation algorithm, PTETRAD, for unstructured tetrahedral meshes (based on the serial code TETRAD) is described and analysed.  ...  The first author also thanks the UK EPSRC for financial support under grants GR/84915 and GR/L73104.  ... 
doi:10.1002/(sici)1096-9128(19991210)11:14<863::aid-cpe464>;2-k fatcat:r5gavp6oz5e5vnmnyxoxcsgola
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