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A New Approach to Automatic Memory Banking using Trace-Based Address Mining

Yuan Zhou, Khalid Musa Al-Hawaj, Zhiru Zhang
2017 Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '17  
Recent years have seen an increased deployment of FPGAs as programmable accelerators for improving the performance and energy efficiency of compute-intensive applications.  ...  Our experiments on Xilinx FPGAs show that TraceBanking achieves competitive performance and resource usage compared to the state-of-the-art across a set of real-life benchmarks with affine memory accesses  ...  FPGA ' 17 , 17 February 22-24, 2017, Monterey, CA, USA c 2017 ACM.  ... 
doi:10.1145/3020078.3021734 fatcat:7xl2bvkf3jdbnjfe3dfgkc622i

Run-Time defect tolerance using JBits

Prasanna Sundararajan, Steven A. Guccione
2001 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays - FPGA '01  
One barrier to acceptance is that existing defect tolerance techniques for FPGAs have tended to rely on either modifications to device architectures or modifications to design tools.  ...  While FPGA devices appear to be well suited to providing defect tolerance, practical application of existing research and techniques has been somewhat elusive.  ...  FPGA 2001 , 2001 February 11-13, 2001, Monterey, CA, USA Copyright 2001 ACM 1-58113-341-3/01/0002 ..$5.00 Figure 1 : 1 Defect Tolerant RTP Core Scheme Figure 3 :Figure 4 : 34 Skip Skip Column Mode  ... 
doi:10.1145/360276.360346 dblp:conf/fpga/SundararajanG01 fatcat:oytmm44ezbeqfoyly3sdh6vq7y

A Case for Work-stealing on FPGAs with OpenCL Atomics

Nadesh Ramanathan, John Wickerson, Felix Winterstein, George A. Constantinides
2016 Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '16  
This demonstrates that the ability to do load balancing at run-time can outweigh the drawback of using 'expensive' atomics on FPGAs.  ...  We provide a case study of work-stealing, a popular method for run-time load balancing, on FPGAs.  ...  The support of the EPSRC Centre for Doctoral Training in High Performance Embedded and Distributed Systems (HiPEDS, Grant Reference EP/L016796/1) and grants EP/I020357/1 and EP/K015168/1, the Royal Academy  ... 
doi:10.1145/2847263.2847343 dblp:conf/fpga/RamanathanWWC16 fatcat:3gzdq6bnmjhw7jrmqjqzsljvo4

ADAM

Ho-Cheung Ng, Shuanglong Liu, Wayne Luk
2018 Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '18  
Experimental results show that ADAM can reduce compilation time by around 5 times when each design is 95% similar to the others, and the compilation time is reduced from 1 hour to 10 minutes in the case  ...  selection of the original designs at runtime.  ...  ACKNOWLEDGMENT The support of the Lee Family Scholarship, the EU Horizon 2020 Research and Innovation Programme under grant agreement number 671653 and the UK EPSRC (EP/L00058X/1, EP/L016796/1, EP/N031768  ... 
doi:10.1145/3174243.3174247 dblp:conf/fpga/NgLL18 fatcat:xugrgidax5hm7eounibvahlbja

Field Programmable Gate Array Applications—A Scientometric Review

Juan Ruiz-Rosero, Gustavo Ramirez-Gonzalez, Rahul Khanna
2019 Computation  
Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems  ...  These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers' navigation systems  ...  In Proceedings of the 1998 ACM/SIGDA 6th International Symposium on Field Programmable Gate Arrays, FPGA, Monterey, CA, USA, 22-24 February 1998. 47. Singh, A.; Prasad, A.; Talwar, Y.  ... 
doi:10.3390/computation7040063 fatcat:wxtatzsvvnfopghdfl25hcfc2a

Logic Synthesis [chapter]

2017 Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology  
ACKNOWLEDGMENT e authors thank Vladimir Yutsis for his helpful feedback on Section 1.5.2.  ...  Impact of FPGA architecture on resource sharing in high-level synthesis, in ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2012, pp. 111-114. 42.  ...  ., Optimizing SDRAM bandwidth for custom FPGA loop accelerators, in ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2012, pp. 195-204. SYNTHESIS: LOGIC OPTIMIZATION 52.  ... 
doi:10.1201/9781315215112-13 fatcat:me52zpnxyfcczh3choo2p4zulm