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Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors
[chapter]
Lecture Notes in Computer Science
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To achieve high resource utilization for multi-issue Digital Signal Processors (DSPs), production compilers commonly include variants of the iterative modulo scheduling algorithm. ...
In response to this resource underutilization problem, this paper describes a compiler preprocessing strategy that capitalizes on two techniques for effective modulo scheduling, referred to as cloning1 ...
We thank the anonymous reviewers for their constructive comments and suggestions. ...
doi:10.1007/978-3-540-71229-9_2
dblp:conf/cc/ChoAUP07
fatcat:pkluddm7gjd7dlovvohrglqr2i
Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs
[chapter]
2006
Lecture Notes in Computer Science
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An iterative modulo scheduling is very important for compilers targeting high performance multi-issue digital signal processors. ...
restrict modulo scheduling freedom and therefore, become a limiting factor of the iterative modulo scheduler. ...
To measure the feasibility and effectiveness of our preprocessing technique, the StarCore SC1400 DSP processor is used as the representative for multi-issue based DSPs.
Definition 2. ...
doi:10.1007/11807964_75
fatcat:7mej5ane65anrb5swhz5cncwoa
Hierarchical coarse-grained stream compilation for software defined radio
2007
Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems - CASES '07
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The operation throughput requirements of current third-generation (3G) wireless protocols are an order of magnitude higher than the capabilities of modern digital signal processors. ...
Because of the streaming nature of SDR protocols, we adapted an existing instruction-level software pipelining technique, modulo scheduling, for coarse-grained compilation. ...
Our results have shown that our compiler is able to generate multi-processor schedules that get near linear speedups for various MPSoC system configurations, while dealing effectively with the tight memory ...
doi:10.1145/1289881.1289903
dblp:conf/cases/LinKMM07
fatcat:n2rkbxygjfaiblioqg5nwwqqua
High-Performance Buffer Mapping to Exploit DRAM Concurrency in Multiprocessor DSP Systems
2009
2009 IEEE/IFIP International Symposium on Rapid System Prototyping
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Design methodologies and tools based on the synchronous dataflow (SDF) model of computation have proven useful for rapid prototyping and implementation of digital signal processing (DSP) applications on ...
In this paper, to help alleviate the memory wall problem, we propose a novel, highperformance buffer mapping policy for SDF-represented DSP applications on multiprocessor systems that support the shared-memory ...
Bambha of the US Army Research Laboratory for providing his scheduling simulator. This research was supported in part by grant number 0325119 from the U.S. National Science Foundation. ...
doi:10.1109/rsp.2009.34
dblp:conf/rsp/LeeBW09
fatcat:ssa7ubxw2vaihlgw6pfhd2b46m
Application driven embedded system design
2007
Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems - CASES '07
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Core specialization has been employed in the embedded space and is likely to play an important role in future heterogeneous multi-core architectures as well. ...
The crux of the problem is the need to co-schedule the often conflicting constraints of data access, data movement, and computation. ...
Using digital signal processors (DSPs) or general purpose processors (GPPs) handles the ASIC inflexibility problem but often fails to meet both performance and power constraints. ...
doi:10.1145/1289881.1289902
dblp:conf/cases/RamaniD07
fatcat:ybbpppvjcjgkrivcw54lz66buu
Modulo graph embedding
2006
Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems - CASES '06
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On average, a compute utilization of 56-68% is achieved for a set of loop kernels across three 4x4 CGRA designs. ...
Modulo graph embedding is effective because it can take into account the communication structure of the loop body during mapping. ...
CONCLUSION This paper proposes modulo graph embedding, an effective modulo scheduling technique for CGRAs. ...
doi:10.1145/1176760.1176778
dblp:conf/cases/ParkFKM06
fatcat:cejmnre3crg2xfniulpxkxexz4
Edge-centric modulo scheduling for coarse-grained reconfigurable architectures
2008
Proceedings of the 17th international conference on Parallel architectures and compilation techniques - PACT '08
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To systematically attack this problem, we take an edge-centric approach to modulo scheduling that focuses on the routing problem as its primary objective. ...
Traditional schedulers focus on the placement of operations in time and space. ...
Simulated annealing is an effective strategy for CGRA scheduling, but its high performance comes at the cost of slow compile time. ...
doi:10.1145/1454115.1454140
dblp:conf/IEEEpact/ParkFMOKK08
fatcat:uvwjgh3rkzgifeh64jgalnexkq
Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation
1996
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Ravel-XL is a single-board hardware accelerator for gate-level digital logic simulation. It uses a standard levelized-code approach to statically schedule gate evaluations. ...
A Ravel-XL board consisting of the processor chip and local instruction and data memory can simulate up to one billion gates at a rate of approximately 6.6 million gate evaluations per second. ...
Acknowledgments The authors would like to thank Jeff Bell for his work on the Ravel-XL compiler, and also the anonymous reviewers for their helpful suggestions and constructive criticism. ...
doi:10.1109/92.486085
fatcat:jgbwizetvvey7lqfj3zn4y3es4
0 Instruction Set Architecture
[chapter]
2003
Digital Design and Computer Organization
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Two main techniques based on different approaches are used for creating software pipelined schedules: modulo scheduling [46, 70] , and unroll-and-jam [12] . ...
multi-processor system. ...
3 Found initial prototype mapped on : core_3b 4 Loading information from APEX file ... 5 Initial prototype has 3 issue -slots 6 7 Searching for best 'ed ' fitness solution ... 8 Using ' issue - ...
doi:10.1201/b12403-15
fatcat:mygaz2meibgljew5tzvmuw6x5i
Secure and Reliable ML-based Disease Detection for a Medical Wireless Body Sensor Networks
2022
International Journal of Biology and Biomedical Engineering
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For disease detection, our research provide insight into several physiological signals, including the ElectroCardioGram (ECG), ElectroMyoGram (EMG), and Blood Pressure (BP), where the security is achieved ...
Similarly, to obtain a reasonable range of reliability, a classification procedure based on supervised Machine Learning (ML) techniques is used. ...
The authors would like to thank DAAD for the support of the joint cooperation. They draw up many thanks to the European exchange program for supporting their work. ...
doi:10.46300/91011.2022.16.26
fatcat:x52cqhbw7bbcln4q5fkk4n6chm
Compiling Scilab to high performance embedded multicore systems
2013
Microprocessors and microsystems
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a Scilab-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from a high level of abstraction. ...
The Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of ...
of reconfigurable systems, and their associated CAD tools, and secondly on some aspects of signal processing like finite arithmetic effects and cooperation in mobile systems. ...
doi:10.1016/j.micpro.2013.07.004
fatcat:pdh6kpwp25galdrdtvpv45l2cy
A Survey on Hardware Implementations of Elliptic Curve Cryptosystems
[article]
2017
arXiv
pre-print
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In addition, a classification of the previous works in terms of scalability, flexibility, performance and cost effectiveness is provided. ...
Therefore, in these categories to have a better presentation and comparison, the implementations are presented and distinguished based on type of finite fields. ...
Figure 27 : Structure of pseudo-multi-core ECC processor in [93] . ...
arXiv:1710.08336v1
fatcat:g3gpz5lzgvc27fboa5tv4kdhze
Abstracts of Current Computer Literature
1968
IEEE transactions on computers
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This paper describes the philosophy of a high-speed digital processor designed for the analysis of all types of analog biological signals in an on-line and real-time manner. ...
improving search strategy. ...
doi:10.1109/tc.1968.226455
fatcat:syhwt24pazahde6pjqsan47epq
Dependable embedded systems
2008
2008 6th IEEE International Conference on Industrial Informatics
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The authors also would like to thank STMicroelectronics for the cooperation on FDSOI technology. ...
It was a tremendous help to see to possibilities of FDSOI in silicon very early on. ...
can be used for an early estimation of temperature-dependent aging of multi/many-core processors. ...
doi:10.1109/indin.2008.4618103
fatcat:hal6brsgsjg5rlo3u5xil46pxi
Automatic License Plate Recognition using OpenCV
2014
International Journal of Computer Applications Technology and Research
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Automatic license plate recognition (ALPR) has complex characteristics due to diverse effects such as of light and speed. Most of the ALPR systems are built using proprietary tools like Matlab. ...
In Backup Overlapping, for example, two primary copies are scheduled on processor 1 and processor 3 and their backups are scheduled in an overlapping manner on processor 2. ...
Backup Schedules After the earliest possible start time for a backup on all processor is determined, the time window that this backup can be scheduled on all processor is determined which is between this ...
doi:10.7753/ijcatr0312.1001
fatcat:ystj5xcmxnf2hg5fwp2lsvp5ny
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