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Predictive sequential associative cache

B. Calder, D. Grunwald, J. Emer
Proceedings. Second International Symposium on High-Performance Computer Architecture  
In this paper, we propose a cache design that provides the same miss rate as a two-way set associative cache, but with a access time closer to a direct-mapped cache.  ...  As with other designs, a traditional direct-mapped cache is conceptually partitioned into multiple banks, and the blocks in each set are probed, or examined, sequentially.  ...  sequential associative caches.  ... 
doi:10.1109/hpca.1996.501190 dblp:conf/hpca/CalderGE96 fatcat:o2hzm7mr35d5jbof2uffoucrku

Phased set associative cache design for reduced power consumption

Rajesh Kannan Megalingam, K.B Deepu, Iype P. Joseph, Vandana Vikram
2009 2009 2nd IEEE International Conference on Computer Science and Information Technology  
set associative cache architecture.  ...  The results show an average of 41% reduction in power consumption as compared to the conventional sequential set associative cache and an average of 21% power reduction as compared to conventional parallel  ...  WAY PREDICTING SET ASSOCIATIVE CACHE ARCHITECTURE The way-predicting cache speculatively chooses one way before starting the normal cache-access process, and then accesses the predicted way [3] If the  ... 
doi:10.1109/iccsit.2009.5234663 fatcat:o4s4wzuk7baozawbp2ekuke7bu

Instruction cache prefetching using multilevel branch prediction [chapter]

Alexander V. Veidenbaum
1997 Lecture Notes in Computer Science  
Existing instruction cache prefetching methods are strictly sequential and cannot do that due to their inability to prefetch past branches.  ...  By keeping branch history and branch target addresses we predict a future PC several branches past the current branch.  ...  Fully-associative prediction Next we analyze the performance of a fully-associative predictor with table sizes of 64, 256 and 512, and prediction levels of 1, 2 and 3.  ... 
doi:10.1007/bfb0024203 fatcat:kmjl556oczbjfjngrukhfbqfvi

NON-SEQUENTIAL INSTRUCTION CACHE PREFETCHING FOR MULTIPLE–ISSUE PROCESSORS

ALEXANDER V. VEIDENBAUM, QINGBO ZHAO, ABDUHL SHAMEER
1999 International journal of high speed computing  
The problem of high primary I-cache miss rates has been traditionally addressed via sequential instruction prefetching.  ...  Only blocking I-caches are considered, although lockup-free caches can help to combine branch prediction and prefetching. This paper makes three major contributions.  ...  A cache configuration is represented by a triplet (cache size, line size, associativity).  ... 
doi:10.1142/s0129053399000065 fatcat:epd6pr67orbahlcrysjl5snz2q

Instruction cache prefetching directed by branch prediction

J. -C. Chiu, R. -M. Shiu, S. -A. Chi, C. P. Chung
1999 IEE Proceedings - Computers and digital Techniques  
Simulation results show that for commercial benchmarks, BIB prefetching outperforms traditional sequential prefetching by 7% and other prediction table based prefetching methods by 17% on average.  ...  The authors have developed a new instruction cache prefetching method in which the prefetch is directed by the prediction on branches, called branch instruction based (BIB) prefetching; in which the prefetch  ...  The symbol 'associativity size' is used to indicate the associativity and size of the instruction cache.  ... 
doi:10.1049/ip-cdt:19990310 fatcat:nc26hxqgvfajloh53g6nom5h6q

HoLiSwap: Reducing Wire Energy in L1 Caches [article]

Yatish Turakhia, Subhasis Das, Tor M. Aamodt, William J. Dally
2017 arXiv   pre-print
This provides up to 44 energy (1.82 rate and 0.13 way-prediction.  ...  Our method exploits this difference in wire energy to dynamically identify hot lines and swap them to the nearest physical way in a set-associative L1 cache.  ...  We also evaluated HoLiSwap for different L1-D cache sizes for SEQUENTIAL. The associativity of the cache (4-way) and the sizes of data subarrays (8KB) were kept unchanged.  ... 
arXiv:1701.03878v1 fatcat:khc5gxkfizb65hgjt4yeaohwve

Improving Performance of Single-Path Code through a Time-Predictable Memory Hierarchy

Bekim Cilku, Wolfgang Puffitsch, Daniel Prokesch, Martin Schoeberl, Peter Puschner
2017 2017 IEEE 20th International Symposium on Real-Time Distributed Computing (ISORC)  
The new memory hierarchy reduces both the cache-miss penalty time and the cachemiss rate on the instruction cache.  ...  We propose a time-predictable memory hierarchy with a prefetcher that exploits the predictability of execution traces in single-path code to speed up code execution.  ...  Time-predictable Prefetching Scheme for Single-path Code For the sake of efficiency and time-predictability, the prefetcher combines both sequential and non-sequential prefetching.  ... 
doi:10.1109/isorc.2017.17 dblp:conf/isorc/CilkuPPSP17 fatcat:2tmykvnuzjfgtbi7swhxetxmme

WHOLE: A low energy I-Cache with separate way history

Zichao Xie, Dong Tong, Xu Cheng
2009 2009 IEEE International Conference on Computer Design  
Set-associative instruction caches achieve low miss rates at the expense of significant energy dissipation.  ...  The WHOLE-Cache design not only achieves a significant portion of energy reduction by effectively reducing dynamic energy dissipation of set-associative instruction cache, but also leads to no additional  ...  ACKNOWLEDGMENTS We would like to thank Li Xian Feng, Lu Junlin of MPRC for their help with the paper review, and Shang Zheng, Shi Yunfeng for the help with the cache model.  ... 
doi:10.1109/iccd.2009.5413162 dblp:conf/iccd/XieTC09 fatcat:5vrw5uzob5chlm4mvllqphe2be

Different access mechanisms for set-associative cache architecture for reduced power consumption

Ankita Pandey, Sanjay Sharma
2013 International Journal of Electronics Letters  
By predicting for the sequential instruction flow and non-sequential one respectively, high way prediction hit rate was achieved.  ...  sequential set-associative cache architecture.  ... 
doi:10.1080/21681724.2013.828269 fatcat:j7s4yipmvna7vcvc4rbz2xe7ga

Web-log mining for predictive web caching

Qiang Yang, H.H. Zhang
2003 IEEE Transactions on Knowledge and Data Engineering  
In our approach, we develop an n-gram-based prediction algorithm that can predict future Web requests. The prediction model is then used to extend the well-known GDSF caching policy.  ...  We empirically show that the system performance is improved using the predictive-caching approach.  ...  In our approach, Web logs are used to train sequential association rules to predict Web users' browsing behavior.  ... 
doi:10.1109/tkde.2003.1209022 fatcat:7wexositrzfalkxa3hrnsobdlq

Designing a time predictable memory hierarchy for single-path code

Bekim Cilku, Peter Puschner
2015 ACM SIGBED Review  
We propose a new instuction-prefetch scheme and cache organization that utilize the "knowledge of the future" properties of single-path code to reduce the main memory access latency and the number of cache  ...  The single-path conversion overcomes this difficulty by transforming all unpredictable branch alternatives in the code to a sequential code structure with a single execution trace.  ...  Instructions in the cache can be mapped to any location (fully associative), to a dedicated set of cache lines (set-associative) or to only one cache line location (directmapped).  ... 
doi:10.1145/2782753.2782755 fatcat:yczv4adi45hapg3vbujdmtu3dy

Exploiting program hotspots and code sequentiality for instruction cache leakage management

J. S. Hu, A. Nadgir, N. Vijaykrishnan, M. J. Irwin, M. Kandemir
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
Second, we exploit code sequentiality in implementing a Just-In-Time Activation (JITA) that transitions cache lines to active mode just before they are accessed.  ...  In this work, we focus on instruction caches and tailor two techniques that exploit the two major factors that shape the instruction access behavior, namely, hotspot execution and sequentiality.  ...  Further, we would like a predictive turn-on mechanism to support the sequentiality of instruction cache accesses.  ... 
doi:10.1145/871604.871606 fatcat:bxsvjiyqjfa6hkasbjbt7gwvdu

Exploiting program hotspots and code sequentiality for instruction cache leakage management

J. S. Hu, A. Nadgir, N. Vijaykrishnan, M. J. Irwin, M. Kandemir
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
Second, we exploit code sequentiality in implementing a Just-In-Time Activation (JITA) that transitions cache lines to active mode just before they are accessed.  ...  In this work, we focus on instruction caches and tailor two techniques that exploit the two major factors that shape the instruction access behavior, namely, hotspot execution and sequentiality.  ...  Further, we would like a predictive turn-on mechanism to support the sequentiality of instruction cache accesses.  ... 
doi:10.1145/871506.871606 dblp:conf/islped/HuNVIK03 fatcat:7xvkweiiyfekfaluol3mah3usq

Ring data location prediction scheme for Non-Uniform Cache Architectures

Sayaka Akioka, Feihui Li, Konrad Malkowski, Padma Raghavan, Mahmut Kandemir, Mary Jane Irwin
2008 2008 IEEE International Conference on Computer Design  
We show that our LAB ring prediction scheme reduces L2 energy significantly over the sequential and parallel schemes, while maintaining similar performance.  ...  Non-Uniform Cache Architecture (NUCA) is one of proposed solutions to reducing the average access latency in such cache designs.  ...  They proposed associated cache management policies such as cache line placement, search, and migration. Incremental and multicast searches are two methods commonly used to locate a cache line.  ... 
doi:10.1109/iccd.2008.4751936 dblp:conf/iccd/AkiokaLMRKI08 fatcat:gitdxmgoqbdvxctwmi6qihhdmm

Parallelism in the front-end

Paramjit S. Oberoi, Gurindar S. Sohi
2003 SIGARCH Computer Architecture News  
Parallelism also enhances latency tolerance: a parallel front-end loses only 6% performance as the cache size is decreased from 128 KB to 8 KB, compared with a 50-65% performance loss for sequential fetch  ...  Compared with an equivalently-sized trace cache, our technique increases cache bandwidth utilization by 17%, front-end throughput by 20%, and performance by 5%.  ...  Branches are predicted using a trace predictor. TC represents a 2-way set associative trace cache with a maximum trace size of 16 instructions.  ... 
doi:10.1145/871656.859645 fatcat:vl4vrj36hfbtpp6zbgwojotaqm
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